Search

Kannan Shanmugasundaram

Examiner (ID: 10064, Phone: (571)270-7763 , Office: P/2158 )

Most Active Art Unit
2158
Art Unit(s)
4152, 2158, 2168
Total Applications
619
Issued Applications
408
Pending Applications
63
Abandoned Applications
166

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16844465 [patent_doc_number] => 11016549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Method, apparatus, and system for power management on a CPU die via clock request messaging protocol [patent_app_type] => utility [patent_app_number] => 15/870629 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 15606 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/870629
Method, apparatus, and system for power management on a CPU die via clock request messaging protocol Jan 11, 2018 Issued
Array ( [id] => 15757143 [patent_doc_number] => 10620682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => System, apparatus and method for processor-external override of hardware performance state control of a processor [patent_app_type] => utility [patent_app_number] => 15/849995 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 18760 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849995 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849995
System, apparatus and method for processor-external override of hardware performance state control of a processor Dec 20, 2017 Issued
Array ( [id] => 14472789 [patent_doc_number] => 20190188039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SYSTEM AND METHOD FOR MANAGING SYSTEM MEMORY INTEGRITY IN SUSPENDED ELECTRONIC CONTROL UNITS [patent_app_type] => utility [patent_app_number] => 15/845254 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845254 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845254
System and method for managing system memory integrity in suspended electronic control units Dec 17, 2017 Issued
Array ( [id] => 16949971 [patent_doc_number] => 20210208663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => POWER GOVERNANCE OF PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 16/650782 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16650782 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/650782
Power governance of processing unit Dec 14, 2017 Issued
Array ( [id] => 17468947 [patent_doc_number] => 11275424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Method for operating a device having a switchable power saving mode for reducing its power consumption [patent_app_type] => utility [patent_app_number] => 16/472563 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5084 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16472563 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/472563
Method for operating a device having a switchable power saving mode for reducing its power consumption Dec 13, 2017 Issued
Array ( [id] => 14415811 [patent_doc_number] => 20190173749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => PLATFORM SPECIFIC CONFIGURATIONS SETUP INTERFACE FOR SERVICE PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/832214 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15832214 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/832214
Platform specific configurations setup interface for service processor Dec 4, 2017 Issued
Array ( [id] => 12803575 [patent_doc_number] => 20180159695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => START CONTROL DEVICE, INFORMATION PROCESSING SYSTEM AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM [patent_app_type] => utility [patent_app_number] => 15/818827 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15818827 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/818827
START CONTROL DEVICE, INFORMATION PROCESSING SYSTEM AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM Nov 20, 2017 Abandoned
Array ( [id] => 14644241 [patent_doc_number] => 10366869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Active feedback control of subsystems of a process module [patent_app_type] => utility [patent_app_number] => 15/818590 [patent_app_country] => US [patent_app_date] => 2017-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 17653 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15818590 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/818590
Active feedback control of subsystems of a process module Nov 19, 2017 Issued
Array ( [id] => 14886349 [patent_doc_number] => 10423212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Techniques for adjusting computing device sleep states using onboard sensors and learned user behaviors [patent_app_type] => utility [patent_app_number] => 15/817113 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 16118 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817113 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/817113
Techniques for adjusting computing device sleep states using onboard sensors and learned user behaviors Nov 16, 2017 Issued
Array ( [id] => 15231041 [patent_doc_number] => 10503241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Providing energy information to memory [patent_app_type] => utility [patent_app_number] => 15/815209 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7428 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15815209 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/815209
Providing energy information to memory Nov 15, 2017 Issued
Array ( [id] => 17260974 [patent_doc_number] => 20210373959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => TIME RELEASED DATA [patent_app_type] => utility [patent_app_number] => 16/638216 [patent_app_country] => US [patent_app_date] => 2017-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16638216 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/638216
TIME RELEASED DATA Nov 6, 2017 Abandoned
Array ( [id] => 12688135 [patent_doc_number] => 20180121211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => SYSTEM AND METHOD FOR DEVICE INTEROPERABILITY AND SYNCHRONIZATION [patent_app_type] => utility [patent_app_number] => 15/788411 [patent_app_country] => US [patent_app_date] => 2017-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7797 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15788411 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/788411
System and method for device interoperability and synchronization Oct 18, 2017 Issued
Array ( [id] => 15399077 [patent_doc_number] => 10540195 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-21 [patent_title] => Synchronizing settings associated with virtual computing environments [patent_app_type] => utility [patent_app_number] => 15/784149 [patent_app_country] => US [patent_app_date] => 2017-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15784149 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/784149
Synchronizing settings associated with virtual computing environments Oct 14, 2017 Issued
Array ( [id] => 12187306 [patent_doc_number] => 20180046242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'LOW POWER TIMING, CONFIGURING, AND SCHEDULING' [patent_app_type] => utility [patent_app_number] => 15/728453 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13053 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728453 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728453
Low power timing, configuring, and scheduling Oct 8, 2017 Issued
Array ( [id] => 15284165 [patent_doc_number] => 10514745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Techniques to predict memory bandwidth demand for a memory device [patent_app_type] => utility [patent_app_number] => 15/721423 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9682 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721423 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721423
Techniques to predict memory bandwidth demand for a memory device Sep 28, 2017 Issued
Array ( [id] => 17698742 [patent_doc_number] => 11372464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Adaptive parameterization for maximum current protection [patent_app_type] => utility [patent_app_number] => 15/719481 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9745 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719481 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/719481
Adaptive parameterization for maximum current protection Sep 27, 2017 Issued
Array ( [id] => 14106547 [patent_doc_number] => 20190094949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => HIERARCHICAL POWER MANAGEMENT UNIT FOR LOW POWER AND LOW DUTY CYCLE DEVICES [patent_app_type] => utility [patent_app_number] => 15/719483 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719483 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/719483
Hierarchical power management unit for low power and low duty cycle devices Sep 27, 2017 Issued
Array ( [id] => 14106501 [patent_doc_number] => 20190094926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => MULTI-CRITERIA POWER MANAGEMENT SCHEME FOR POOLED ACCELERATOR ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 15/718451 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718451 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/718451
Multi-criteria power management scheme for pooled accelerator architectures Sep 27, 2017 Issued
Array ( [id] => 16045593 [patent_doc_number] => 10684667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Dynamic battery power management based on battery internal impedance [patent_app_type] => utility [patent_app_number] => 15/719431 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9687 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719431 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/719431
Dynamic battery power management based on battery internal impedance Sep 27, 2017 Issued
Array ( [id] => 15284171 [patent_doc_number] => 10514748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Reactive power management for non-volatile memory controllers [patent_app_type] => utility [patent_app_number] => 15/716961 [patent_app_country] => US [patent_app_date] => 2017-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4963 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716961 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716961
Reactive power management for non-volatile memory controllers Sep 26, 2017 Issued
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