
Kannan Shanmugasundaram
Examiner (ID: 10064, Phone: (571)270-7763 , Office: P/2158 )
| Most Active Art Unit | 2158 |
| Art Unit(s) | 4152, 2158, 2168 |
| Total Applications | 619 |
| Issued Applications | 408 |
| Pending Applications | 63 |
| Abandoned Applications | 166 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4591097
[patent_doc_number] => 07827430
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-02
[patent_title] => 'Integrated circuit with interpolation to avoid harmonic interference'
[patent_app_type] => utility
[patent_app_number] => 11/800208
[patent_app_country] => US
[patent_app_date] => 2007-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 6966
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/827/07827430.pdf
[firstpage_image] =>[orig_patent_app_number] => 11800208
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/800208 | Integrated circuit with interpolation to avoid harmonic interference | May 3, 2007 | Issued |
Array
(
[id] => 912354
[patent_doc_number] => 07334153
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-02-19
[patent_title] => 'Low-speed DLL employing a digital phase interpolator based upon a high-speed clock'
[patent_app_type] => utility
[patent_app_number] => 11/738913
[patent_app_country] => US
[patent_app_date] => 2007-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 4752
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 123
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/334/07334153.pdf
[firstpage_image] =>[orig_patent_app_number] => 11738913
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/738913 | Low-speed DLL employing a digital phase interpolator based upon a high-speed clock | Apr 22, 2007 | Issued |
Array
(
[id] => 836323
[patent_doc_number] => 07398407
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-08
[patent_title] => 'Method and apparatus for on-demand power management'
[patent_app_type] => utility
[patent_app_number] => 11/784866
[patent_app_country] => US
[patent_app_date] => 2007-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/398/07398407.pdf
[firstpage_image] =>[orig_patent_app_number] => 11784866
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/784866 | Method and apparatus for on-demand power management | Apr 8, 2007 | Issued |
Array
(
[id] => 38335
[patent_doc_number] => 07788519
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-31
[patent_title] => 'Method, system, and apparatus for improving multi-core processor performance'
[patent_app_type] => utility
[patent_app_number] => 11/686861
[patent_app_country] => US
[patent_app_date] => 2007-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2131
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/788/07788519.pdf
[firstpage_image] =>[orig_patent_app_number] => 11686861
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/686861 | Method, system, and apparatus for improving multi-core processor performance | Mar 14, 2007 | Issued |
Array
(
[id] => 4990699
[patent_doc_number] => 20070157040
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-05
[patent_title] => 'PERSONAL ELECTRONIC DEVICE WITH APPLIANCE DRIVE FEATURES'
[patent_app_type] => utility
[patent_app_number] => 11/686115
[patent_app_country] => US
[patent_app_date] => 2007-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
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[patent_no_of_words] => 12807
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[pdf_file] => publications/A1/0157/20070157040.pdf
[firstpage_image] =>[orig_patent_app_number] => 11686115
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/686115 | PERSONAL ELECTRONIC DEVICE WITH APPLIANCE DRIVE FEATURES | Mar 13, 2007 | Abandoned |
Array
(
[id] => 868890
[patent_doc_number] => 07370216
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-06
[patent_title] => 'Conserving power by reducing voltage supplied to an instruction-processing portion of a processor'
[patent_app_type] => utility
[patent_app_number] => 11/715092
[patent_app_country] => US
[patent_app_date] => 2007-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/370/07370216.pdf
[firstpage_image] =>[orig_patent_app_number] => 11715092
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/715092 | Conserving power by reducing voltage supplied to an instruction-processing portion of a processor | Mar 6, 2007 | Issued |
Array
(
[id] => 911696
[patent_doc_number] => 07325789
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-02-05
[patent_title] => 'Box beam terminals'
[patent_app_type] => utility
[patent_app_number] => 11/682442
[patent_app_country] => US
[patent_app_date] => 2007-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 5493
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/325/07325789.pdf
[firstpage_image] =>[orig_patent_app_number] => 11682442
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/682442 | Box beam terminals | Mar 5, 2007 | Issued |
Array
(
[id] => 4700251
[patent_doc_number] => 20080222435
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-11
[patent_title] => 'POWER MANAGEMENT IN A POWER-CONSTRAINED PROCESSING SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 11/681818
[patent_app_country] => US
[patent_app_date] => 2007-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6553
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0222/20080222435.pdf
[firstpage_image] =>[orig_patent_app_number] => 11681818
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/681818 | Power management in a power-constrained processing system | Mar 4, 2007 | Issued |
Array
(
[id] => 7689951
[patent_doc_number] => 20070234082
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'COMPUTER SYSTEM WITH NON-SUPPORT HYPER-TRANSPORT PROCESSOR AND CONTROLLING METHOD OF HYPER-TRANSPORT BUS THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/681917
[patent_app_country] => US
[patent_app_date] => 2007-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2994
[patent_no_of_claims] => 20
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[pdf_file] => publications/A1/0234/20070234082.pdf
[firstpage_image] =>[orig_patent_app_number] => 11681917
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/681917 | Computer system with non-support hyper-transport processor and controlling method of hyper-transport bus thereof | Mar 4, 2007 | Issued |
Array
(
[id] => 5086999
[patent_doc_number] => 20070277050
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-29
[patent_title] => 'Conserving Power in Processing Systems'
[patent_app_type] => utility
[patent_app_number] => 11/682215
[patent_app_country] => US
[patent_app_date] => 2007-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0277/20070277050.pdf
[firstpage_image] =>[orig_patent_app_number] => 11682215
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/682215 | Conserving power in processing systems | Mar 4, 2007 | Issued |
Array
(
[id] => 4673830
[patent_doc_number] => 20080211458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-04
[patent_title] => 'CHARGING DISPLAY SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 11/680699
[patent_app_country] => US
[patent_app_date] => 2007-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[pdf_file] => publications/A1/0211/20080211458.pdf
[firstpage_image] =>[orig_patent_app_number] => 11680699
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/680699 | Charging display system | Feb 28, 2007 | Issued |
Array
(
[id] => 9241
[patent_doc_number] => 07814345
[patent_country] => US
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[patent_issue_date] => 2010-10-12
[patent_title] => 'Gate drive voltage selection for a voltage regulator'
[patent_app_type] => utility
[patent_app_number] => 11/680524
[patent_app_country] => US
[patent_app_date] => 2007-02-28
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[pdf_file] => patents/07/814/07814345.pdf
[firstpage_image] =>[orig_patent_app_number] => 11680524
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/680524 | Gate drive voltage selection for a voltage regulator | Feb 27, 2007 | Issued |
Array
(
[id] => 87756
[patent_doc_number] => 07743264
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-22
[patent_title] => 'Method and system of controlling operational state of a computer system via power button of a peripheral device'
[patent_app_type] => utility
[patent_app_number] => 11/617901
[patent_app_country] => US
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[pdf_file] => patents/07/743/07743264.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617901 | Method and system of controlling operational state of a computer system via power button of a peripheral device | Dec 28, 2006 | Issued |
Array
(
[id] => 37604
[patent_doc_number] => 07793118
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[patent_issue_date] => 2010-09-07
[patent_title] => 'Electronic device with a plurality of charging modes'
[patent_app_type] => utility
[patent_app_number] => 11/618064
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/618064 | Electronic device with a plurality of charging modes | Dec 28, 2006 | Issued |
Array
(
[id] => 4754885
[patent_doc_number] => 20080162961
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[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'Portable Player, Power Management Apparatus, And Power Management Algorithm Thereof'
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[firstpage_image] =>[orig_patent_app_number] => 11617196
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617196 | Portable Player, Power Management Apparatus, And Power Management Algorithm Thereof | Dec 27, 2006 | Abandoned |
Array
(
[id] => 5024751
[patent_doc_number] => 20070150718
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-28
[patent_title] => 'INFORMATION PROCESSING APPARATUS AND METHOD FOR USING RECONFIGURABLE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/616751
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[pdf_file] => publications/A1/0150/20070150718.pdf
[firstpage_image] =>[orig_patent_app_number] => 11616751
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/616751 | Information processing apparatus and method for using reconfigurable device | Dec 26, 2006 | Issued |
Array
(
[id] => 4550004
[patent_doc_number] => 07873847
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-18
[patent_title] => 'Method of power state control for a server blade in a blade—server chassis system'
[patent_app_type] => utility
[patent_app_number] => 11/616501
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/616501 | Method of power state control for a server blade in a blade—server chassis system | Dec 26, 2006 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/616687 | Power management block for use in a non-volatile memory system | Dec 26, 2006 | Issued |
Array
(
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[patent_title] => 'METHOD AND APPARATUS OF COLLECTING TIMER TICKS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/616667 | Method and apparatus of collecting timer ticks | Dec 26, 2006 | Issued |
Array
(
[id] => 4984406
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[patent_title] => 'Processor and methods to reduce power consumption of processor components'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/637064 | Processor and methods to reduce power consumption of processor components | Dec 11, 2006 | Abandoned |