
Kannan Shanmugasundaram
Examiner (ID: 10064, Phone: (571)270-7763 , Office: P/2158 )
| Most Active Art Unit | 2158 |
| Art Unit(s) | 4152, 2158, 2168 |
| Total Applications | 619 |
| Issued Applications | 408 |
| Pending Applications | 63 |
| Abandoned Applications | 166 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4979014
[patent_doc_number] => 20070220249
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-20
[patent_title] => 'DATA STRUCTURE AND METHOD FOR MANAGING MODULES ASSOCIATED WITH A KERNEL'
[patent_app_type] => utility
[patent_app_number] => 11/605102
[patent_app_country] => US
[patent_app_date] => 2006-11-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/605102 | Data structure and method for managing modules associated with a kernel | Nov 27, 2006 | Issued |
Array
(
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[patent_doc_number] => 07689855
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[patent_kind] => B2
[patent_issue_date] => 2010-03-30
[patent_title] => 'Clock supplying apparatus and control method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/559115 | Clock supplying apparatus and control method thereof | Nov 12, 2006 | Issued |
Array
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[patent_title] => 'Standby Mode for Power Management'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/559388 | Standby mode for power management | Nov 12, 2006 | Issued |
Array
(
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[patent_issue_date] => 2010-03-23
[patent_title] => 'Dynamic voltage scaling method of CPU using workload estimator and computer readable medium storing the method'
[patent_app_type] => utility
[patent_app_number] => 11/559117
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Array
(
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[patent_title] => 'Method and system for receiving a software image from a customer for installation into a computer system'
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Array
(
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[patent_title] => 'Idle Mode for Power Management'
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Array
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[id] => 4540208
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[patent_title] => 'Power amplifier'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/558585 | Power amplifier | Nov 9, 2006 | Issued |
Array
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[id] => 5081388
[patent_doc_number] => 20070124612
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[patent_issue_date] => 2007-05-31
[patent_title] => 'METHOD AND SYSTEM FOR CONTROLLING A MIXED ARRAY OF POINT-OF-LOAD REGULATORS THROUGH A BUS TRANSLATOR'
[patent_app_type] => utility
[patent_app_number] => 11/558848
[patent_app_country] => US
[patent_app_date] => 2006-11-10
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[pdf_file] => publications/A1/0124/20070124612.pdf
[firstpage_image] =>[orig_patent_app_number] => 11558848
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/558848 | Method and system for controlling a mixed array of point-of-load regulators through a bus translator | Nov 9, 2006 | Issued |
Array
(
[id] => 4969816
[patent_doc_number] => 20070109818
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-17
[patent_title] => 'SWITCHING MODE POWER SUPPLY'
[patent_app_type] => utility
[patent_app_number] => 11/558428
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/558428 | Switching mode power supply | Nov 8, 2006 | Issued |
Array
(
[id] => 4577095
[patent_doc_number] => 07823001
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[patent_issue_date] => 2010-10-26
[patent_title] => 'Latency adjustment between integrated circuit chips'
[patent_app_type] => utility
[patent_app_number] => 11/553532
[patent_app_country] => US
[patent_app_date] => 2006-10-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/553532 | Latency adjustment between integrated circuit chips | Oct 26, 2006 | Issued |
Array
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[id] => 423711
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[patent_title] => 'Task-oriented processing as an auxiliary to primary computing environments'
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Array
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[id] => 5052884
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[patent_title] => 'Instantaneously restartable clocks and their use such as in connecting clocked subsystems using clockless sequencing networks'
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Array
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[id] => 7726334
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[patent_title] => 'Power management for buses in cmos circuits'
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Array
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Array
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Array
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Array
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