Search

Kannan Shanmugasundaram

Examiner (ID: 10064, Phone: (571)270-7763 , Office: P/2158 )

Most Active Art Unit
2158
Art Unit(s)
4152, 2158, 2168
Total Applications
619
Issued Applications
408
Pending Applications
63
Abandoned Applications
166

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7030732 [patent_doc_number] => 20050022037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Method, system, and apparatus for an efficient power dissipation' [patent_app_type] => utility [patent_app_number] => 10/624366 [patent_app_country] => US [patent_app_date] => 2003-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1373 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20050022037.pdf [firstpage_image] =>[orig_patent_app_number] => 10624366 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/624366
Method, system, and apparatus for an efficient power dissipation Jul 20, 2003 Issued
Array ( [id] => 671571 [patent_doc_number] => 07096351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-22 [patent_title] => 'Single-chip microcomputer and boot region switching method thereof' [patent_app_type] => utility [patent_app_number] => 10/615817 [patent_app_country] => US [patent_app_date] => 2003-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7983 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/096/07096351.pdf [firstpage_image] =>[orig_patent_app_number] => 10615817 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/615817
Single-chip microcomputer and boot region switching method thereof Jul 8, 2003 Issued
Array ( [id] => 7370965 [patent_doc_number] => 20040027181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Clock multiplying PLL circuit' [patent_app_type] => new [patent_app_number] => 10/606225 [patent_app_country] => US [patent_app_date] => 2003-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5760 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20040027181.pdf [firstpage_image] =>[orig_patent_app_number] => 10606225 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/606225
Clock multiplying PLL circuit Jun 25, 2003 Abandoned
Array ( [id] => 568613 [patent_doc_number] => 07171550 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-30 [patent_title] => 'Data structure and method for managing modules associated with a kernel' [patent_app_type] => utility [patent_app_number] => 10/464092 [patent_app_country] => US [patent_app_date] => 2003-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5220 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/171/07171550.pdf [firstpage_image] =>[orig_patent_app_number] => 10464092 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/464092
Data structure and method for managing modules associated with a kernel Jun 17, 2003 Issued
Array ( [id] => 749524 [patent_doc_number] => 07032122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Data transfer system capable of transferring data at high transfer speed' [patent_app_type] => utility [patent_app_number] => 10/462755 [patent_app_country] => US [patent_app_date] => 2003-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9568 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/032/07032122.pdf [firstpage_image] =>[orig_patent_app_number] => 10462755 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/462755
Data transfer system capable of transferring data at high transfer speed Jun 16, 2003 Issued
Array ( [id] => 739691 [patent_doc_number] => 07039797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Method of allocating a basic input/output system to a shadow memory' [patent_app_type] => utility [patent_app_number] => 10/462756 [patent_app_country] => US [patent_app_date] => 2003-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5061 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/039/07039797.pdf [firstpage_image] =>[orig_patent_app_number] => 10462756 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/462756
Method of allocating a basic input/output system to a shadow memory Jun 16, 2003 Issued
Array ( [id] => 645629 [patent_doc_number] => 07124308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Control of reproduction apparatus and distribution apparatus based on remaining power of battery' [patent_app_type] => utility [patent_app_number] => 10/454706 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15704 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124308.pdf [firstpage_image] =>[orig_patent_app_number] => 10454706 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/454706
Control of reproduction apparatus and distribution apparatus based on remaining power of battery Jun 3, 2003 Issued
Array ( [id] => 8158299 [patent_doc_number] => 08171331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Memory channel having deskew separate from redrive' [patent_app_type] => utility [patent_app_number] => 10/456206 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 12095 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/171/08171331.pdf [firstpage_image] =>[orig_patent_app_number] => 10456206 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/456206
Memory channel having deskew separate from redrive Jun 3, 2003 Issued
Array ( [id] => 518786 [patent_doc_number] => 07203848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-10 [patent_title] => 'Electrical apparatus, program for controlling electrical apparatus, and method for controlling electrical apparatus' [patent_app_type] => utility [patent_app_number] => 10/448346 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/203/07203848.pdf [firstpage_image] =>[orig_patent_app_number] => 10448346 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448346
Electrical apparatus, program for controlling electrical apparatus, and method for controlling electrical apparatus May 29, 2003 Issued
Array ( [id] => 7266706 [patent_doc_number] => 20040243858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Low power mode for device power management' [patent_app_type] => new [patent_app_number] => 10/447852 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4345 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20040243858.pdf [firstpage_image] =>[orig_patent_app_number] => 10447852 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/447852
Low power mode for device power management May 28, 2003 Issued
Array ( [id] => 5747285 [patent_doc_number] => 20060110216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Joint' [patent_app_type] => utility [patent_app_number] => 10/440170 [patent_app_country] => US [patent_app_date] => 2003-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1679 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20060110216.pdf [firstpage_image] =>[orig_patent_app_number] => 10440170 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/440170
Joint May 18, 2003 Issued
Array ( [id] => 96888 [patent_doc_number] => 07734904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Resetting a system in response to changes of component settings' [patent_app_type] => utility [patent_app_number] => 10/423451 [patent_app_country] => US [patent_app_date] => 2003-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2858 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/734/07734904.pdf [firstpage_image] =>[orig_patent_app_number] => 10423451 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/423451
Resetting a system in response to changes of component settings Apr 24, 2003 Issued
Array ( [id] => 666998 [patent_doc_number] => 07103763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Storage and access of configuration data in nonvolatile memory of a logically-partitioned computer' [patent_app_type] => utility [patent_app_number] => 10/422213 [patent_app_country] => US [patent_app_date] => 2003-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 7036 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/103/07103763.pdf [firstpage_image] =>[orig_patent_app_number] => 10422213 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/422213
Storage and access of configuration data in nonvolatile memory of a logically-partitioned computer Apr 23, 2003 Issued
Array ( [id] => 404213 [patent_doc_number] => 07293165 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-06 [patent_title] => 'BMC-hosted boot ROM interface' [patent_app_type] => utility [patent_app_number] => 10/406131 [patent_app_country] => US [patent_app_date] => 2003-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2274 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/293/07293165.pdf [firstpage_image] =>[orig_patent_app_number] => 10406131 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/406131
BMC-hosted boot ROM interface Apr 2, 2003 Issued
Array ( [id] => 524998 [patent_doc_number] => 07197657 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-27 [patent_title] => 'BMC-hosted real-time clock and non-volatile RAM replacement' [patent_app_type] => utility [patent_app_number] => 10/406130 [patent_app_country] => US [patent_app_date] => 2003-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2298 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/197/07197657.pdf [firstpage_image] =>[orig_patent_app_number] => 10406130 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/406130
BMC-hosted real-time clock and non-volatile RAM replacement Apr 2, 2003 Issued
Array ( [id] => 7353064 [patent_doc_number] => 20040193860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Methods and apparatus to export information from hardware devices' [patent_app_type] => new [patent_app_number] => 10/395729 [patent_app_country] => US [patent_app_date] => 2003-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4177 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20040193860.pdf [firstpage_image] =>[orig_patent_app_number] => 10395729 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/395729
Methods and apparatus to export information from hardware devices Mar 23, 2003 Abandoned
Array ( [id] => 7154439 [patent_doc_number] => 20040172571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'Buffer circuit and method' [patent_app_type] => new [patent_app_number] => 10/377304 [patent_app_country] => US [patent_app_date] => 2003-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5289 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20040172571.pdf [firstpage_image] =>[orig_patent_app_number] => 10377304 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/377304
Buffer circuit and method Feb 27, 2003 Issued
Array ( [id] => 7154430 [patent_doc_number] => 20040172566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'Mechanism for reducing power consumption of a transmitter/receiver circuit' [patent_app_type] => new [patent_app_number] => 10/376413 [patent_app_country] => US [patent_app_date] => 2003-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3917 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20040172566.pdf [firstpage_image] =>[orig_patent_app_number] => 10376413 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/376413
Mechanism for reducing power consumption of a transmitter/receiver circuit Feb 27, 2003 Issued
Array ( [id] => 469476 [patent_doc_number] => 07240222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-03 [patent_title] => 'Using ACPI power button signal for remotely controlling the power of a PC' [patent_app_type] => utility [patent_app_number] => 10/375929 [patent_app_country] => US [patent_app_date] => 2003-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3372 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240222.pdf [firstpage_image] =>[orig_patent_app_number] => 10375929 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/375929
Using ACPI power button signal for remotely controlling the power of a PC Feb 26, 2003 Issued
Array ( [id] => 7154435 [patent_doc_number] => 20040172569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'Integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section' [patent_app_type] => new [patent_app_number] => 10/375575 [patent_app_country] => US [patent_app_date] => 2003-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3699 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20040172569.pdf [firstpage_image] =>[orig_patent_app_number] => 10375575 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/375575
Integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section Feb 26, 2003 Issued
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