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Kannan Shanmugasundaram

Examiner (ID: 10064, Phone: (571)270-7763 , Office: P/2158 )

Most Active Art Unit
2158
Art Unit(s)
4152, 2158, 2168
Total Applications
619
Issued Applications
408
Pending Applications
63
Abandoned Applications
166

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 975536 [patent_doc_number] => 06938177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-30 [patent_title] => 'Multi-chip module smart controller' [patent_app_type] => utility [patent_app_number] => 10/028556 [patent_app_country] => US [patent_app_date] => 2001-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/938/06938177.pdf [firstpage_image] =>[orig_patent_app_number] => 10028556 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/028556
Multi-chip module smart controller Dec 18, 2001 Issued
Array ( [id] => 992781 [patent_doc_number] => 06920578 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-19 [patent_title] => 'Method and apparatus for transferring data between a slower clock domain and a faster clock domain in which one of the clock domains is bandwidth limited' [patent_app_type] => utility [patent_app_number] => 10/026305 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4014 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/920/06920578.pdf [firstpage_image] =>[orig_patent_app_number] => 10026305 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/026305
Method and apparatus for transferring data between a slower clock domain and a faster clock domain in which one of the clock domains is bandwidth limited Dec 17, 2001 Issued
Array ( [id] => 794337 [patent_doc_number] => 06983384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Graphics controller and power management method for use in the same' [patent_app_type] => utility [patent_app_number] => 09/941861 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5622 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/983/06983384.pdf [firstpage_image] =>[orig_patent_app_number] => 09941861 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941861
Graphics controller and power management method for use in the same Aug 29, 2001 Issued
Array ( [id] => 765063 [patent_doc_number] => 07016989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-21 [patent_title] => 'Fast 16 bit, split transaction I/O bus' [patent_app_type] => utility [patent_app_number] => 09/471445 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8778 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/016/07016989.pdf [firstpage_image] =>[orig_patent_app_number] => 09471445 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471445
Fast 16 bit, split transaction I/O bus Dec 22, 1999 Issued
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