Karin M. Reichle

Array ( [id] => 5188535 [patent_doc_number] => 20070166843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Method of repairing a light-emitting device and method of manufacturing a light-emitting device' [patent_app_type] => utility [patent_app_number] => 11/726551 [patent_app_country] => US [patent_app_date] => 2007-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 17367 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20070166843.pdf [firstpage_image] =>[orig_patent_app_number] => 11726551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5060336 [patent_doc_number] => 20070221973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/688536 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5683 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20070221973.pdf [firstpage_image] =>[orig_patent_app_number] => 11688536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5186026 [patent_doc_number] => 20070164333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'INTEGRATED MIS PHOTOSENSITIVE DEVICE USING CONTINUOUS FILMS' [patent_app_type] => utility [patent_app_number] => 11/687495 [patent_app_country] => US [patent_app_date] => 2007-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6569 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20070164333.pdf [firstpage_image] =>[orig_patent_app_number] => 11687495 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5245146 [patent_doc_number] => 20070241380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 11/686885 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 6689 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20070241380.pdf [firstpage_image] =>[orig_patent_app_number] => 11686885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4568771 [patent_doc_number] => 07858466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Different-voltage device manufactured by a CMOS compatible process and high-voltage device used in the different-voltage device' [patent_app_type] => utility [patent_app_number] => 11/682621 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1636 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/858/07858466.pdf [firstpage_image] =>[orig_patent_app_number] => 11682621 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4723902 [patent_doc_number] => 20080203443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Independently-Double-Gated Transistor Memory (IDGM)' [patent_app_type] => utility [patent_app_number] => 11/678026 [patent_app_country] => US [patent_app_date] => 2007-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8151 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20080203443.pdf [firstpage_image] =>[orig_patent_app_number] => 11678026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5296645 [patent_doc_number] => 20090011571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'WAFER WORKING METHOD' [patent_app_type] => utility [patent_app_number] => 12/281590 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7666 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20090011571.pdf [firstpage_image] =>[orig_patent_app_number] => 12281590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8846670 [patent_doc_number] => 08455854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Nonvolatile memory device including amorphous alloy metal oxide layer and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/704365 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3409 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11704365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 557063 [patent_doc_number] => 07470552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-30 [patent_title] => 'Method for production of MRAM elements' [patent_app_type] => utility [patent_app_number] => 11/700958 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1841 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/470/07470552.pdf [firstpage_image] =>[orig_patent_app_number] => 11700958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 322524 [patent_doc_number] => 07517756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Flash memory array with increased coupling between floating and control gates' [patent_app_type] => utility [patent_app_number] => 11/668306 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 7080 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/517/07517756.pdf [firstpage_image] =>[orig_patent_app_number] => 11668306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 411605 [patent_doc_number] => 07282445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Multiple seed layers for interconnects' [patent_app_type] => utility [patent_app_number] => 11/654478 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8256 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/282/07282445.pdf [firstpage_image] =>[orig_patent_app_number] => 11654478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 810537 [patent_doc_number] => 07417294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-26 [patent_title] => 'Microelectronic imaging units and methods of manufacturing microelectronic imaging units' [patent_app_type] => utility [patent_app_number] => 11/653861 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4039 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/417/07417294.pdf [firstpage_image] =>[orig_patent_app_number] => 11653861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4932994 [patent_doc_number] => 20080003769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Method for fabricating semiconductor device having trench isolation layer' [patent_app_type] => utility [patent_app_number] => 11/647929 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1773 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20080003769.pdf [firstpage_image] =>[orig_patent_app_number] => 11647929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4933012 [patent_doc_number] => 20080003787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/617628 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1777 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20080003787.pdf [firstpage_image] =>[orig_patent_app_number] => 11617628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4988786 [patent_doc_number] => 20070155125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'METHOD FOR FORMING SHALLOW TRENCH ISOLATION OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/617209 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1389 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20070155125.pdf [firstpage_image] =>[orig_patent_app_number] => 11617209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5022939 [patent_doc_number] => 20070148905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'METHOD OF FORMING A TRENCH ISOLATION LAYER IN A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/616758 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1521 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148905.pdf [firstpage_image] =>[orig_patent_app_number] => 11616758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4772008 [patent_doc_number] => 20080057666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/616018 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1449 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20080057666.pdf [firstpage_image] =>[orig_patent_app_number] => 11616018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4879873 [patent_doc_number] => 20080153256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Methods and systems for nitridation of STI liner oxide in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/644339 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20080153256.pdf [firstpage_image] =>[orig_patent_app_number] => 11644339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 359664 [patent_doc_number] => 07485543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Method for manufacturing semiconductor device with overlay vernier' [patent_app_type] => utility [patent_app_number] => 11/642598 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 1494 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/485/07485543.pdf [firstpage_image] =>[orig_patent_app_number] => 11642598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 908253 [patent_doc_number] => 07332794 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-19 [patent_title] => 'System and method for providing a self heating adjustable TiSi2 resistor' [patent_app_type] => utility [patent_app_number] => 11/639019 [patent_app_country] => US [patent_app_date] => 2006-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/332/07332794.pdf [firstpage_image] =>[orig_patent_app_number] => 11639019 [rel_patent_id] =>[rel_patent_doc_number] =>)