
Karin M. Reichle
Examiner (ID: 5558, Phone: (571)272-4936 , Office: P/3992 )
| Most Active Art Unit | 3761 |
| Art Unit(s) | 3727, 3735, 2899, 3992, 3305, 3308, 3761 |
| Total Applications | 1663 |
| Issued Applications | 775 |
| Pending Applications | 227 |
| Abandoned Applications | 671 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5625551
[patent_doc_number] => 20060264056
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-23
[patent_title] => 'Method and apparatus for fabricating a memory device with a dielectric etch stop layer'
[patent_app_type] => utility
[patent_app_number] => 11/495499
[patent_app_country] => US
[patent_app_date] => 2006-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7052
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0264/20060264056.pdf
[firstpage_image] =>[orig_patent_app_number] => 11495499
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/495499 | Method and apparatus for fabricating a memory device with a dielectric etch stop layer | Jul 27, 2006 | Issued |
Array
(
[id] => 487509
[patent_doc_number] => 07217987
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-15
[patent_title] => 'Semiconductor device and manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/493829
[patent_app_country] => US
[patent_app_date] => 2006-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 50
[patent_figures_cnt] => 58
[patent_no_of_words] => 21887
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/217/07217987.pdf
[firstpage_image] =>[orig_patent_app_number] => 11493829
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/493829 | Semiconductor device and manufacturing the same | Jul 26, 2006 | Issued |
Array
(
[id] => 4657680
[patent_doc_number] => 20080026541
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-31
[patent_title] => 'AIR-GAP INTERCONNECT STRUCTURES WITH SELECTIVE CAP'
[patent_app_type] => utility
[patent_app_number] => 11/460019
[patent_app_country] => US
[patent_app_date] => 2006-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6182
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0026/20080026541.pdf
[firstpage_image] =>[orig_patent_app_number] => 11460019
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/460019 | AIR-GAP INTERCONNECT STRUCTURES WITH SELECTIVE CAP | Jul 25, 2006 | Abandoned |
Array
(
[id] => 102151
[patent_doc_number] => 07727906
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-06-01
[patent_title] => 'H2-based plasma treatment to eliminate within-batch and batch-to-batch etch drift'
[patent_app_type] => utility
[patent_app_number] => 11/493679
[patent_app_country] => US
[patent_app_date] => 2006-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5525
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/727/07727906.pdf
[firstpage_image] =>[orig_patent_app_number] => 11493679
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/493679 | H2-based plasma treatment to eliminate within-batch and batch-to-batch etch drift | Jul 25, 2006 | Issued |
Array
(
[id] => 5625476
[patent_doc_number] => 20060263981
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-23
[patent_title] => 'DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators'
[patent_app_type] => utility
[patent_app_number] => 11/492638
[patent_app_country] => US
[patent_app_date] => 2006-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 11577
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0263/20060263981.pdf
[firstpage_image] =>[orig_patent_app_number] => 11492638
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/492638 | DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators | Jul 24, 2006 | Abandoned |
Array
(
[id] => 5049101
[patent_doc_number] => 20070029645
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-08
[patent_title] => 'High permeability layered films to reduce noise in high speed interconnects'
[patent_app_type] => utility
[patent_app_number] => 11/492253
[patent_app_country] => US
[patent_app_date] => 2006-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 15796
[patent_no_of_claims] => 66
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0029/20070029645.pdf
[firstpage_image] =>[orig_patent_app_number] => 11492253
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/492253 | High permeability layered films to reduce noise in high speed interconnects | Jul 24, 2006 | Abandoned |
Array
(
[id] => 4657679
[patent_doc_number] => 20080026540
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-31
[patent_title] => 'Integration for buried epitaxial stressor'
[patent_app_type] => utility
[patent_app_number] => 11/492649
[patent_app_country] => US
[patent_app_date] => 2006-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3519
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0026/20080026540.pdf
[firstpage_image] =>[orig_patent_app_number] => 11492649
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/492649 | Integration for buried epitaxial stressor | Jul 24, 2006 | Issued |
Array
(
[id] => 5733047
[patent_doc_number] => 20060258164
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'Method and apparatus for fabricating a memory device with a dielectric etch stop layer'
[patent_app_type] => utility
[patent_app_number] => 11/492138
[patent_app_country] => US
[patent_app_date] => 2006-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7029
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0258/20060258164.pdf
[firstpage_image] =>[orig_patent_app_number] => 11492138
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/492138 | Method and apparatus for fabricating a memory device with a dielectric etch stop layer | Jul 23, 2006 | Issued |
Array
(
[id] => 394325
[patent_doc_number] => 07298024
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-20
[patent_title] => 'Transparent amorphous carbon structure in semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 11/458642
[patent_app_country] => US
[patent_app_date] => 2006-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 27
[patent_no_of_words] => 7896
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/298/07298024.pdf
[firstpage_image] =>[orig_patent_app_number] => 11458642
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/458642 | Transparent amorphous carbon structure in semiconductor devices | Jul 18, 2006 | Issued |
Array
(
[id] => 246994
[patent_doc_number] => 07585746
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-08
[patent_title] => 'Process integration scheme of SONOS technology'
[patent_app_type] => utility
[patent_app_number] => 11/485949
[patent_app_country] => US
[patent_app_date] => 2006-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 3342
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/585/07585746.pdf
[firstpage_image] =>[orig_patent_app_number] => 11485949
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/485949 | Process integration scheme of SONOS technology | Jul 11, 2006 | Issued |
Array
(
[id] => 456434
[patent_doc_number] => 07244645
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-17
[patent_title] => 'Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers and related structures'
[patent_app_type] => utility
[patent_app_number] => 11/479551
[patent_app_country] => US
[patent_app_date] => 2006-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 6789
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/244/07244645.pdf
[firstpage_image] =>[orig_patent_app_number] => 11479551
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/479551 | Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers and related structures | Jun 29, 2006 | Issued |
Array
(
[id] => 4933002
[patent_doc_number] => 20080003777
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-03
[patent_title] => 'Nickel Tin Bonding System for Semiconductor Wafers and Devices'
[patent_app_type] => utility
[patent_app_number] => 11/428158
[patent_app_country] => US
[patent_app_date] => 2006-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7068
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20080003777.pdf
[firstpage_image] =>[orig_patent_app_number] => 11428158
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/428158 | Nickel tin bonding system for semiconductor wafers and devices | Jun 29, 2006 | Issued |
Array
(
[id] => 8294882
[patent_doc_number] => 08222672
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-17
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/476205
[patent_app_country] => US
[patent_app_date] => 2006-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 26
[patent_no_of_words] => 4548
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11476205
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/476205 | Semiconductor device and manufacturing method thereof | Jun 27, 2006 | Issued |
Array
(
[id] => 5202221
[patent_doc_number] => 20070023700
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-01
[patent_title] => 'Manufacturing method of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/474499
[patent_app_country] => US
[patent_app_date] => 2006-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6482
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0023/20070023700.pdf
[firstpage_image] =>[orig_patent_app_number] => 11474499
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/474499 | Manufacturing method of semiconductor device | Jun 25, 2006 | Issued |
Array
(
[id] => 162265
[patent_doc_number] => 07670886
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-02
[patent_title] => 'Method for fabricating polysilicon film'
[patent_app_type] => utility
[patent_app_number] => 11/472858
[patent_app_country] => US
[patent_app_date] => 2006-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2268
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/670/07670886.pdf
[firstpage_image] =>[orig_patent_app_number] => 11472858
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/472858 | Method for fabricating polysilicon film | Jun 21, 2006 | Issued |
Array
(
[id] => 5730240
[patent_doc_number] => 20060255354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/455950
[patent_app_country] => US
[patent_app_date] => 2006-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 10841
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0255/20060255354.pdf
[firstpage_image] =>[orig_patent_app_number] => 11455950
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/455950 | Semiconductor device and method for manufacturing the same | Jun 19, 2006 | Issued |
Array
(
[id] => 363434
[patent_doc_number] => 07482245
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-01-27
[patent_title] => 'Stress profile modulation in STI gap fill'
[patent_app_type] => utility
[patent_app_number] => 11/471958
[patent_app_country] => US
[patent_app_date] => 2006-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6546
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/482/07482245.pdf
[firstpage_image] =>[orig_patent_app_number] => 11471958
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/471958 | Stress profile modulation in STI gap fill | Jun 19, 2006 | Issued |
Array
(
[id] => 352605
[patent_doc_number] => 07491626
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-17
[patent_title] => 'Layer growth using metal film and/or islands'
[patent_app_type] => utility
[patent_app_number] => 11/424999
[patent_app_country] => US
[patent_app_date] => 2006-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 5387
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/491/07491626.pdf
[firstpage_image] =>[orig_patent_app_number] => 11424999
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/424999 | Layer growth using metal film and/or islands | Jun 18, 2006 | Issued |
Array
(
[id] => 5019578
[patent_doc_number] => 20070145544
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-28
[patent_title] => 'Method for producing a grid cap with a locally increased dielectric constant'
[patent_app_type] => utility
[patent_app_number] => 11/454468
[patent_app_country] => US
[patent_app_date] => 2006-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4755
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0145/20070145544.pdf
[firstpage_image] =>[orig_patent_app_number] => 11454468
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/454468 | Method for producing a grid cap with a locally increased dielectric constant | Jun 15, 2006 | Issued |
Array
(
[id] => 5141954
[patent_doc_number] => 20070004170
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-04
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/451519
[patent_app_country] => US
[patent_app_date] => 2006-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 11685
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0004/20070004170.pdf
[firstpage_image] =>[orig_patent_app_number] => 11451519
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/451519 | Method of manufacturing semiconductor device | Jun 12, 2006 | Issued |