Search

Karl E. Group

Examiner (ID: 17110, Phone: (571)272-1368 , Office: P/1731 )

Most Active Art Unit
1731
Art Unit(s)
1793, 2899, 1731, 1755, 1108
Total Applications
4063
Issued Applications
3169
Pending Applications
125
Abandoned Applications
770

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16773909 [patent_doc_number] => 10985030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 16/684817 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 12812 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684817 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684817
Method for manufacturing semiconductor device Nov 14, 2019 Issued
Array ( [id] => 17339510 [patent_doc_number] => 20220005841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/618909 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16618909 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/618909
Manufacturing method for array substrate Nov 11, 2019 Issued
Array ( [id] => 16617515 [patent_doc_number] => 20210036168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (MOS) CAPACITOR [patent_app_type] => utility [patent_app_number] => 16/674002 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16674002 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/674002
COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (MOS) CAPACITOR Nov 4, 2019 Abandoned
Array ( [id] => 15503235 [patent_doc_number] => 20200051806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => VFET DEVICES WITH ILD PROTECTION [patent_app_type] => utility [patent_app_number] => 16/659691 [patent_app_country] => US [patent_app_date] => 2019-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16659691 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/659691
VFET devices with ILD protection Oct 21, 2019 Issued
Array ( [id] => 17203487 [patent_doc_number] => 20210343582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => METHODS OF MANUFACTURING A TRANSISTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/284524 [patent_app_country] => US [patent_app_date] => 2019-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17284524 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/284524
METHODS OF MANUFACTURING A TRANSISTOR DEVICE Oct 13, 2019 Pending
Array ( [id] => 16653306 [patent_doc_number] => 10930498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Methods for producing nanowire stack GAA device with inner spacer [patent_app_type] => utility [patent_app_number] => 16/598275 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 7306 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598275 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/598275
Methods for producing nanowire stack GAA device with inner spacer Oct 9, 2019 Issued
Array ( [id] => 15745689 [patent_doc_number] => 20200111734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => LOGIC DRIVE BASED ON MULTICHIP PACKAGE USING INTERCONNECTION BRIDGE [patent_app_type] => utility [patent_app_number] => 16/590981 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 86690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 774 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16590981 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/590981
Logic drive based on multichip package using interconnection bridge Oct 1, 2019 Issued
Array ( [id] => 15443271 [patent_doc_number] => 20200035819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/589117 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589117 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/589117
Semiconductor device Sep 29, 2019 Issued
Array ( [id] => 17303047 [patent_doc_number] => 20210398886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => Chip Package Positioning and Fixing Structure [patent_app_type] => utility [patent_app_number] => 17/288618 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17288618 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/288618
Chip package positioning and fixing structure Sep 19, 2019 Issued
Array ( [id] => 15332463 [patent_doc_number] => 20200006561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => STRAINED FIN CHANNEL DEVICES [patent_app_type] => utility [patent_app_number] => 16/539294 [patent_app_country] => US [patent_app_date] => 2019-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16539294 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/539294
Method for forming strained fin channel devices Aug 12, 2019 Issued
Array ( [id] => 15503777 [patent_doc_number] => 20200052077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => Needle Cell Trench MOSFET [patent_app_type] => utility [patent_app_number] => 16/537101 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537101 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/537101
Needle cell trench MOSFET Aug 8, 2019 Issued
Array ( [id] => 16402280 [patent_doc_number] => 20200343138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/537158 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537158 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/537158
Method for forming a semiconductor structure with a gate contact plug Aug 8, 2019 Issued
Array ( [id] => 16119743 [patent_doc_number] => 20200211894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME [patent_app_type] => utility [patent_app_number] => 16/537123 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537123 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/537123
Method for forming a fin-based semiconductor structure Aug 8, 2019 Issued
Array ( [id] => 17956400 [patent_doc_number] => 11482513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Heterogeneous substrate bonding for photonic integration [patent_app_type] => utility [patent_app_number] => 16/452212 [patent_app_country] => US [patent_app_date] => 2019-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4390 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16452212 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/452212
Heterogeneous substrate bonding for photonic integration Jun 24, 2019 Issued
Array ( [id] => 16944350 [patent_doc_number] => 11056602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Device, system, and method for selectively tuning nanoparticles with graphene [patent_app_type] => utility [patent_app_number] => 16/447652 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4567 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447652 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447652
Device, system, and method for selectively tuning nanoparticles with graphene Jun 19, 2019 Issued
Array ( [id] => 15300323 [patent_doc_number] => 20190393297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => CAPACITOR BANK STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/447839 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447839 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447839
Capacitor bank structure and semiconductor package structure Jun 19, 2019 Issued
Array ( [id] => 16528877 [patent_doc_number] => 20200402958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/447805 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447805
SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME Jun 19, 2019 Abandoned
Array ( [id] => 16528984 [patent_doc_number] => 20200403065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => VERTICAL FET WITH ASYMMETRIC THRESHOLD VOLTAGE AND CHANNEL THICKNESSES [patent_app_type] => utility [patent_app_number] => 16/447614 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447614 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447614
Vertical FET with asymmetric threshold voltage and channel thicknesses Jun 19, 2019 Issued
Array ( [id] => 15564933 [patent_doc_number] => 20200066878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => METAL OXIDE SEMICONDUCTOR DEVICE CAPABLE OF REDUCING ON-RESISTANCE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/447820 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447820 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447820
METAL OXIDE SEMICONDUCTOR DEVICE CAPABLE OF REDUCING ON-RESISTANCE AND MANUFACTURING METHOD THEREOF Jun 19, 2019 Abandoned
Array ( [id] => 14875983 [patent_doc_number] => 20190288233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/428254 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16428254 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/428254
Display device having sealing grooves May 30, 2019 Issued
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