Search

Karl E. Group

Examiner (ID: 17110)

Most Active Art Unit
1731
Art Unit(s)
1793, 2899, 1731, 1755, 1108
Total Applications
4063
Issued Applications
3169
Pending Applications
125
Abandoned Applications
770

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17500842 [patent_doc_number] => 11289552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Display panel [patent_app_type] => utility [patent_app_number] => 17/185180 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4953 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185180 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185180
Display panel Feb 24, 2021 Issued
Array ( [id] => 17795682 [patent_doc_number] => 20220254774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR BIPOLAR TRANSISTOR STACK WITHIN SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/173611 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173611 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173611
Integrated circuit structure and method for bipolar transistor stack within substrate Feb 10, 2021 Issued
Array ( [id] => 17040896 [patent_doc_number] => 20210257532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => SUPERCONDUCTING BUMP BOND ELECTRICAL CHARACTERIZATION [patent_app_type] => utility [patent_app_number] => 17/168443 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168443 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168443
Superconducting bump bond electrical characterization Feb 4, 2021 Issued
Array ( [id] => 19584161 [patent_doc_number] => 12150308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Semiconductor chip [patent_app_type] => utility [patent_app_number] => 17/160378 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 9447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160378 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160378
Semiconductor chip Jan 27, 2021 Issued
Array ( [id] => 17010926 [patent_doc_number] => 20210242087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => METHOD FOR FABRICATING A DEVICE COMPRISING A PNP BIPOLAR TRANSISTOR AND NPN BIPOLAR TRANSISTOR FOR RADIOFREQUENCY APPLICATIONS [patent_app_type] => utility [patent_app_number] => 17/160598 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160598 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160598
Method for fabricating a device comprising a PNP bipolar transistor and NPN bipolar transistor for radiofrequency applications Jan 27, 2021 Issued
Array ( [id] => 17303176 [patent_doc_number] => 20210399015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/155093 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17155093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/155093
Memory devices Jan 21, 2021 Issued
Array ( [id] => 16827831 [patent_doc_number] => 20210143124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => LOGIC DRIVE BASED ON MULTICHIP PACKAGE USING INTERCONNECTION BRIDGE [patent_app_type] => utility [patent_app_number] => 17/151634 [patent_app_country] => US [patent_app_date] => 2021-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 86701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17151634 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/151634
Logic drive based on multichip package using interconnection bridge Jan 17, 2021 Issued
Array ( [id] => 18593502 [patent_doc_number] => 11742414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Semiconductor device with fins [patent_app_type] => utility [patent_app_number] => 17/247984 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5383 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/247984
Semiconductor device with fins Jan 3, 2021 Issued
Array ( [id] => 18205634 [patent_doc_number] => 11588042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/130590 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5211 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130590 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/130590
Semiconductor device Dec 21, 2020 Issued
Array ( [id] => 18387327 [patent_doc_number] => 11658120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Porogen bonded gap filling material in semiconductor manufacturing [patent_app_type] => utility [patent_app_number] => 17/120672 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120672 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120672
Porogen bonded gap filling material in semiconductor manufacturing Dec 13, 2020 Issued
Array ( [id] => 16731431 [patent_doc_number] => 20210098579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => SCHOTTKY DIODE WITH HIGH BREAKDOWN VOLTAGE AND SURGE CURRENT CAPABILITY USING DOUBLE P-TYPE EPITAXIAL LAYERS [patent_app_type] => utility [patent_app_number] => 17/118451 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118451 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/118451
SCHOTTKY DIODE WITH HIGH BREAKDOWN VOLTAGE AND SURGE CURRENT CAPABILITY USING DOUBLE P-TYPE EPITAXIAL LAYERS Dec 9, 2020 Abandoned
Array ( [id] => 16781670 [patent_doc_number] => 20210118749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => AIR GAP FORMATION BETWEEN GATE SPACER AND EPITAXY STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/113209 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113209
Air gap formation between gate spacer and epitaxy structure Dec 6, 2020 Issued
Array ( [id] => 16873595 [patent_doc_number] => 20210167062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => MICROELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE [patent_app_type] => utility [patent_app_number] => 17/108830 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108830 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108830
MICROELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE Nov 30, 2020 Abandoned
Array ( [id] => 18088604 [patent_doc_number] => 11538743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Microelectronic device with floating pads [patent_app_type] => utility [patent_app_number] => 17/108920 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 7339 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108920 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108920
Microelectronic device with floating pads Nov 30, 2020 Issued
Array ( [id] => 18175150 [patent_doc_number] => 11574867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Non-planar silicided semiconductor electrical fuse [patent_app_type] => utility [patent_app_number] => 17/104078 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5979 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104078 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104078
Non-planar silicided semiconductor electrical fuse Nov 24, 2020 Issued
Array ( [id] => 16752419 [patent_doc_number] => 20210104431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => CONTACT PLUGS FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/101158 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101158 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/101158
Contact plugs for semiconductor device Nov 22, 2020 Issued
Array ( [id] => 18032215 [patent_doc_number] => 11515415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Integrated circuit comprising an NLDMOS transistor [patent_app_type] => utility [patent_app_number] => 17/095003 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2006 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095003 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095003
Integrated circuit comprising an NLDMOS transistor Nov 10, 2020 Issued
Array ( [id] => 17623383 [patent_doc_number] => 11342449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Integrated circuit comprising a junction field effect transistor [patent_app_type] => utility [patent_app_number] => 17/095230 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3176 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095230 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095230
Integrated circuit comprising a junction field effect transistor Nov 10, 2020 Issued
Array ( [id] => 18190714 [patent_doc_number] => 11581316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Semiconductor devices including semiconductor pattern [patent_app_type] => utility [patent_app_number] => 17/092593 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 8907 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17092593 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/092593
Semiconductor devices including semiconductor pattern Nov 8, 2020 Issued
Array ( [id] => 18782261 [patent_doc_number] => 11824027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/092142 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 6124 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17092142 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/092142
Semiconductor package Nov 5, 2020 Issued
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