
Karl E. Group
Examiner (ID: 17110, Phone: (571)272-1368 , Office: P/1731 )
| Most Active Art Unit | 1731 |
| Art Unit(s) | 1793, 2899, 1731, 1755, 1108 |
| Total Applications | 4063 |
| Issued Applications | 3169 |
| Pending Applications | 125 |
| Abandoned Applications | 770 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17303174
[patent_doc_number] => 20210399013
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-23
[patent_title] => MEMORY DEVICE AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/086463
[patent_app_country] => US
[patent_app_date] => 2020-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8731
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17086463
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/086463 | Memory device | Nov 1, 2020 | Issued |
Array
(
[id] => 16631689
[patent_doc_number] => 20210050342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-18
[patent_title] => Semiconductor Device
[patent_app_type] => utility
[patent_app_number] => 17/085661
[patent_app_country] => US
[patent_app_date] => 2020-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10584
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085661
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/085661 | Semiconductor device | Oct 29, 2020 | Issued |
Array
(
[id] => 17583063
[patent_doc_number] => 20220139918
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-05
[patent_title] => Novel Three-Dimensional DRAM Structures
[patent_app_type] => utility
[patent_app_number] => 17/084420
[patent_app_country] => US
[patent_app_date] => 2020-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6959
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -64
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084420
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/084420 | Novel Three-Dimensional DRAM Structures | Oct 28, 2020 | Pending |
Array
(
[id] => 18137318
[patent_doc_number] => 11563007
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-24
[patent_title] => Semiconductor structure with vertical gate transistor
[patent_app_type] => utility
[patent_app_number] => 17/079943
[patent_app_country] => US
[patent_app_date] => 2020-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 30
[patent_no_of_words] => 7929
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17079943
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/079943 | Semiconductor structure with vertical gate transistor | Oct 25, 2020 | Issued |
Array
(
[id] => 16660780
[patent_doc_number] => 20210057417
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-25
[patent_title] => SEMICONDUCTOR DEVICE INCLUDING ACTIVE REGION WITH VARIABLE ATOMIC CONCENTRATION OF OXIDE SEMICONDUCTOR MATERIAL AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/076025
[patent_app_country] => US
[patent_app_date] => 2020-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8430
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17076025
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/076025 | Method of forming a semiconductor device including an active region with variable atomic concentration of oxide semiconductor material | Oct 20, 2020 | Issued |
Array
(
[id] => 17456278
[patent_doc_number] => 11271145
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-08
[patent_title] => Light emitting device
[patent_app_type] => utility
[patent_app_number] => 17/075272
[patent_app_country] => US
[patent_app_date] => 2020-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 9418
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 376
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075272
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/075272 | Light emitting device | Oct 19, 2020 | Issued |
Array
(
[id] => 17551626
[patent_doc_number] => 20220122968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => HETEROJUNCTION BIPOLAR TRANSISTOR WITH BURIED TRAP RICH ISOLATION REGION
[patent_app_type] => utility
[patent_app_number] => 17/075056
[patent_app_country] => US
[patent_app_date] => 2020-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5747
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075056
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/075056 | Heterojunction bipolar transistor with buried trap rich isolation region | Oct 19, 2020 | Issued |
Array
(
[id] => 18156258
[patent_doc_number] => 11569252
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-31
[patent_title] => Method for manufacturing semiconductor structure and capable of controlling thicknesses of dielectric layers
[patent_app_type] => utility
[patent_app_number] => 17/068836
[patent_app_country] => US
[patent_app_date] => 2020-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2458
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 266
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068836
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/068836 | Method for manufacturing semiconductor structure and capable of controlling thicknesses of dielectric layers | Oct 12, 2020 | Issued |
Array
(
[id] => 16586104
[patent_doc_number] => 20210020506
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-21
[patent_title] => METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE AND SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/063012
[patent_app_country] => US
[patent_app_date] => 2020-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6393
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17063012
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/063012 | Method of forming semiconductor device having a dual material redistribution line and semiconductor device | Oct 4, 2020 | Issued |
Array
(
[id] => 17359888
[patent_doc_number] => 20220020684
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-20
[patent_title] => SEMICONDUCTOR DEVICE AND METAL-OXIDE-SEMICONDUCTOR CAPACITOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/034207
[patent_app_country] => US
[patent_app_date] => 2020-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2853
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034207
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/034207 | Semiconductor device and metal-oxide-semiconductor capacitor structure | Sep 27, 2020 | Issued |
Array
(
[id] => 19494340
[patent_doc_number] => 12113064
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-08
[patent_title] => Diode chip
[patent_app_type] => utility
[patent_app_number] => 17/018486
[patent_app_country] => US
[patent_app_date] => 2020-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 41
[patent_no_of_words] => 32290
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 291
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17018486
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/018486 | Diode chip | Sep 10, 2020 | Issued |
Array
(
[id] => 16715934
[patent_doc_number] => 20210083081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => RC IGBT with an IGBT Section and a Diode Section
[patent_app_type] => utility
[patent_app_number] => 17/016498
[patent_app_country] => US
[patent_app_date] => 2020-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14974
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17016498
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/016498 | RC IGBT with an IGBT section and a diode section | Sep 9, 2020 | Issued |
Array
(
[id] => 18403722
[patent_doc_number] => 11665882
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-30
[patent_title] => Semiconductor memory device
[patent_app_type] => utility
[patent_app_number] => 17/012676
[patent_app_country] => US
[patent_app_date] => 2020-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 18
[patent_no_of_words] => 5764
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 317
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17012676
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/012676 | Semiconductor memory device | Sep 3, 2020 | Issued |
Array
(
[id] => 17381085
[patent_doc_number] => 11239117
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-02-01
[patent_title] => Replacement gate dielectric in three-node access device formation for vertical three dimensional (3D) memory
[patent_app_type] => utility
[patent_app_number] => 17/004084
[patent_app_country] => US
[patent_app_date] => 2020-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 34
[patent_no_of_words] => 16474
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004084
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/004084 | Replacement gate dielectric in three-node access device formation for vertical three dimensional (3D) memory | Aug 26, 2020 | Issued |
Array
(
[id] => 16516124
[patent_doc_number] => 20200395382
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-17
[patent_title] => Integrated Assemblies Comprising Ferroelectric Transistors and Non-Ferroelectric Transistors
[patent_app_type] => utility
[patent_app_number] => 17/003813
[patent_app_country] => US
[patent_app_date] => 2020-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8198
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003813
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/003813 | Integrated assemblies comprising ferroelectric transistors and non-ferroelectric transistors | Aug 25, 2020 | Issued |
Array
(
[id] => 18137392
[patent_doc_number] => 11563081
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-24
[patent_title] => Self-aligned gate edge and local interconnect
[patent_app_type] => utility
[patent_app_number] => 17/000729
[patent_app_country] => US
[patent_app_date] => 2020-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 33
[patent_no_of_words] => 8425
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17000729
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/000729 | Self-aligned gate edge and local interconnect | Aug 23, 2020 | Issued |
Array
(
[id] => 16509413
[patent_doc_number] => 20200388669
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-10
[patent_title] => SINUSOIDAL SHAPED CAPACITOR ARCHITECTURE IN OXIDE
[patent_app_type] => utility
[patent_app_number] => 17/000725
[patent_app_country] => US
[patent_app_date] => 2020-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4391
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17000725
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/000725 | SINUSOIDAL SHAPED CAPACITOR ARCHITECTURE IN OXIDE | Aug 23, 2020 | Abandoned |
Array
(
[id] => 17500761
[patent_doc_number] => 11289471
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-29
[patent_title] => Electrostatic discharge device
[patent_app_type] => utility
[patent_app_number] => 17/001009
[patent_app_country] => US
[patent_app_date] => 2020-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2744
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17001009
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/001009 | Electrostatic discharge device | Aug 23, 2020 | Issued |
Array
(
[id] => 16981605
[patent_doc_number] => 20210225842
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-22
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/999378
[patent_app_country] => US
[patent_app_date] => 2020-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6041
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16999378
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/999378 | Semiconductor memory device | Aug 20, 2020 | Issued |
Array
(
[id] => 18131286
[patent_doc_number] => 11557503
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-17
[patent_title] => Method for co-integration of III-V devices with group IV devices
[patent_app_type] => utility
[patent_app_number] => 16/996413
[patent_app_country] => US
[patent_app_date] => 2020-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 20
[patent_no_of_words] => 10483
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16996413
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/996413 | Method for co-integration of III-V devices with group IV devices | Aug 17, 2020 | Issued |