Search

Kaushikkumar A. Desai

Examiner (ID: 8462, Phone: (571)270-7290 , Office: P/3788 )

Most Active Art Unit
3788
Art Unit(s)
3788, 3728, 3735, 4159
Total Applications
461
Issued Applications
162
Pending Applications
0
Abandoned Applications
300

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6727320 [patent_doc_number] => 20030183510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Conductive material for integrated circuit fabrication' [patent_app_type] => new [patent_app_number] => 10/428637 [patent_app_country] => US [patent_app_date] => 2003-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4995 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20030183510.pdf [firstpage_image] =>[orig_patent_app_number] => 10428637 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/428637
Conductive material for integrated circuit fabrication May 1, 2003 Issued
Array ( [id] => 1223715 [patent_doc_number] => 06699757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-02 [patent_title] => 'Method for manufacturing embedded non-volatile memory with sacrificial layers' [patent_app_type] => B1 [patent_app_number] => 10/397497 [patent_app_country] => US [patent_app_date] => 2003-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3471 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/699/06699757.pdf [firstpage_image] =>[orig_patent_app_number] => 10397497 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/397497
Method for manufacturing embedded non-volatile memory with sacrificial layers Mar 25, 2003 Issued
Array ( [id] => 6843284 [patent_doc_number] => 20030148631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Oxidative annealing method for forming etched spin-on-glass (SOG) planarizing layer with uniform etch profile' [patent_app_type] => new [patent_app_number] => 10/361735 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6184 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20030148631.pdf [firstpage_image] =>[orig_patent_app_number] => 10361735 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/361735
Oxidative annealing method for forming etched spin-on-glass (SOG) planarizing layer with uniform etch profile Feb 9, 2003 Abandoned
Array ( [id] => 1205597 [patent_doc_number] => 06716724 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Method of producing 3-5 group compound semiconductor and semiconductor element' [patent_app_type] => B1 [patent_app_number] => 10/337287 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3475 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716724.pdf [firstpage_image] =>[orig_patent_app_number] => 10337287 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337287
Method of producing 3-5 group compound semiconductor and semiconductor element Jan 6, 2003 Issued
Array ( [id] => 6787783 [patent_doc_number] => 20030139022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Gettering of SOI wafers without regions of heavy doping' [patent_app_type] => new [patent_app_number] => 10/337750 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1535 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20030139022.pdf [firstpage_image] =>[orig_patent_app_number] => 10337750 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337750
Gettering of SOI wafers without regions of heavy doping Jan 6, 2003 Abandoned
Array ( [id] => 1239626 [patent_doc_number] => 06686245 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Vertical MOSFET with asymmetric gate structure' [patent_app_type] => B1 [patent_app_number] => 10/324787 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 22 [patent_no_of_words] => 5154 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686245.pdf [firstpage_image] =>[orig_patent_app_number] => 10324787 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/324787
Vertical MOSFET with asymmetric gate structure Dec 19, 2002 Issued
Array ( [id] => 1179922 [patent_doc_number] => 06740558 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'SiGe vertical gate contact for gate conductor post etch treatment' [patent_app_type] => B1 [patent_app_number] => 10/298717 [patent_app_country] => US [patent_app_date] => 2002-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2345 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/740/06740558.pdf [firstpage_image] =>[orig_patent_app_number] => 10298717 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/298717
SiGe vertical gate contact for gate conductor post etch treatment Nov 17, 2002 Issued
Array ( [id] => 1277752 [patent_doc_number] => 06645818 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Method to fabricate dual-metal gate for N- and P-FETs' [patent_app_type] => B1 [patent_app_number] => 10/293577 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2692 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/645/06645818.pdf [firstpage_image] =>[orig_patent_app_number] => 10293577 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/293577
Method to fabricate dual-metal gate for N- and P-FETs Nov 12, 2002 Issued
Array ( [id] => 6870190 [patent_doc_number] => 20030082879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Non-volatile semiconductor memory device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/292265 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13157 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20030082879.pdf [firstpage_image] =>[orig_patent_app_number] => 10292265 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292265
Non-volatile semiconductor memory device and method of manufacturing the same Nov 11, 2002 Issued
Array ( [id] => 7625536 [patent_doc_number] => 06723633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Method for forming multi-layer wiring structure' [patent_app_type] => B2 [patent_app_number] => 10/291456 [patent_app_country] => US [patent_app_date] => 2002-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 4645 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/723/06723633.pdf [firstpage_image] =>[orig_patent_app_number] => 10291456 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/291456
Method for forming multi-layer wiring structure Nov 6, 2002 Issued
Array ( [id] => 6807303 [patent_doc_number] => 20030197242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Structure and fabrication method of electrostatic discharge protection circuit' [patent_app_type] => new [patent_app_number] => 10/259887 [patent_app_country] => US [patent_app_date] => 2002-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3206 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20030197242.pdf [firstpage_image] =>[orig_patent_app_number] => 10259887 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/259887
Structure and fabrication method of electrostatic discharge protection circuit Sep 29, 2002 Abandoned
Array ( [id] => 6787772 [patent_doc_number] => 20030139011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Multigate semiconductor device with vertical channel current and method of fabrication' [patent_app_type] => new [patent_app_number] => 10/254878 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6168 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20030139011.pdf [firstpage_image] =>[orig_patent_app_number] => 10254878 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254878
Multigate semiconductor device with vertical channel current and method of fabrication Sep 25, 2002 Issued
Array ( [id] => 6755849 [patent_doc_number] => 20030003626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Open-cavity semiconductor die package' [patent_app_type] => new [patent_app_number] => 10/231347 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5592 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003626.pdf [firstpage_image] =>[orig_patent_app_number] => 10231347 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/231347
Open-cavity semiconductor die package Aug 29, 2002 Issued
Array ( [id] => 7135210 [patent_doc_number] => 20040043605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'METHOD OF REDUCING OXIDATION OF METAL STRUCTURES USING ION IMPLANTATION, AND DEVICE FORMED BY SUCH METHOD' [patent_app_type] => new [patent_app_number] => 10/229457 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3151 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20040043605.pdf [firstpage_image] =>[orig_patent_app_number] => 10229457 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229457
Method of reducing oxidation of metal structures using ion implantation, and device formed by such method Aug 27, 2002 Issued
Array ( [id] => 6753432 [patent_doc_number] => 20030001208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Methods, structures, and circuits for transistors with gate-to-body capacitive coupling' [patent_app_type] => new [patent_app_number] => 10/228732 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4796 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20030001208.pdf [firstpage_image] =>[orig_patent_app_number] => 10228732 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/228732
Methods, structures, and circuits for transistors with gate-to-body capacitive coupling Aug 26, 2002 Issued
Array ( [id] => 1248253 [patent_doc_number] => 06673701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Atomic layer deposition methods' [patent_app_type] => B1 [patent_app_number] => 10/229887 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3752 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/673/06673701.pdf [firstpage_image] =>[orig_patent_app_number] => 10229887 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229887
Atomic layer deposition methods Aug 26, 2002 Issued
Array ( [id] => 1288918 [patent_doc_number] => 06632745 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Method of forming almost L-shaped spacer for improved ILD gap fill' [patent_app_type] => B1 [patent_app_number] => 10/222387 [patent_app_country] => US [patent_app_date] => 2002-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4731 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/632/06632745.pdf [firstpage_image] =>[orig_patent_app_number] => 10222387 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/222387
Method of forming almost L-shaped spacer for improved ILD gap fill Aug 15, 2002 Issued
Array ( [id] => 1312246 [patent_doc_number] => 06610589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-26 [patent_title] => 'Semiconductor light emitting device and method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 10/163428 [patent_app_country] => US [patent_app_date] => 2002-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3885 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/610/06610589.pdf [firstpage_image] =>[orig_patent_app_number] => 10163428 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163428
Semiconductor light emitting device and method of manufacturing the same Jun 6, 2002 Issued
Array ( [id] => 1177146 [patent_doc_number] => 06743669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Method of reducing leakage using Si3N4 or SiON block dielectric films' [patent_app_type] => B1 [patent_app_number] => 10/164227 [patent_app_country] => US [patent_app_date] => 2002-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3995 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/743/06743669.pdf [firstpage_image] =>[orig_patent_app_number] => 10164227 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/164227
Method of reducing leakage using Si3N4 or SiON block dielectric films Jun 4, 2002 Issued
Array ( [id] => 5844625 [patent_doc_number] => 20020132476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Barrier layer associated with a conductor layer in damascene structures' [patent_app_type] => new [patent_app_number] => 10/137293 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3189 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20020132476.pdf [firstpage_image] =>[orig_patent_app_number] => 10137293 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/137293
Barrier layer associated with a conductor layer in damascene structures May 2, 2002 Issued
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