
Kaushikkumar A. Desai
Examiner (ID: 8462, Phone: (571)270-7290 , Office: P/3788 )
| Most Active Art Unit | 3788 |
| Art Unit(s) | 3788, 3728, 3735, 4159 |
| Total Applications | 461 |
| Issued Applications | 162 |
| Pending Applications | 0 |
| Abandoned Applications | 300 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6727320
[patent_doc_number] => 20030183510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'Conductive material for integrated circuit fabrication'
[patent_app_type] => new
[patent_app_number] => 10/428637
[patent_app_country] => US
[patent_app_date] => 2003-05-02
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[pdf_file] => publications/A1/0183/20030183510.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/428637 | Conductive material for integrated circuit fabrication | May 1, 2003 | Issued |
Array
(
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[patent_doc_number] => 06699757
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[patent_issue_date] => 2004-03-02
[patent_title] => 'Method for manufacturing embedded non-volatile memory with sacrificial layers'
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[patent_app_number] => 10/397497
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Array
(
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[patent_issue_date] => 2003-08-07
[patent_title] => 'Oxidative annealing method for forming etched spin-on-glass (SOG) planarizing layer with uniform etch profile'
[patent_app_type] => new
[patent_app_number] => 10/361735
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/361735 | Oxidative annealing method for forming etched spin-on-glass (SOG) planarizing layer with uniform etch profile | Feb 9, 2003 | Abandoned |
Array
(
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[patent_issue_date] => 2004-04-06
[patent_title] => 'Method of producing 3-5 group compound semiconductor and semiconductor element'
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[patent_app_number] => 10/337287
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Array
(
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Array
(
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Array
(
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[patent_title] => 'SiGe vertical gate contact for gate conductor post etch treatment'
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Array
(
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[patent_title] => 'Method to fabricate dual-metal gate for N- and P-FETs'
[patent_app_type] => B1
[patent_app_number] => 10/293577
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/293577 | Method to fabricate dual-metal gate for N- and P-FETs | Nov 12, 2002 | Issued |
Array
(
[id] => 6870190
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/292265 | Non-volatile semiconductor memory device and method of manufacturing the same | Nov 11, 2002 | Issued |
Array
(
[id] => 7625536
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[patent_title] => 'Method for forming multi-layer wiring structure'
[patent_app_type] => B2
[patent_app_number] => 10/291456
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/291456 | Method for forming multi-layer wiring structure | Nov 6, 2002 | Issued |
Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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