Search

Kaushikkumar A. Desai

Examiner (ID: 8462, Phone: (571)270-7290 , Office: P/3788 )

Most Active Art Unit
3788
Art Unit(s)
3788, 3728, 3735, 4159
Total Applications
461
Issued Applications
162
Pending Applications
0
Abandoned Applications
300

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4331900 [patent_doc_number] => 06329709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Interconnections for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/076334 [patent_app_country] => US [patent_app_date] => 1998-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2547 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329709.pdf [firstpage_image] =>[orig_patent_app_number] => 076334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076334
Interconnections for a semiconductor device May 10, 1998 Issued
Array ( [id] => 4369710 [patent_doc_number] => 06287988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor device manufacturing method, semiconductor device manufacturing apparatus and semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/039980 [patent_app_country] => US [patent_app_date] => 1998-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 87 [patent_no_of_words] => 36559 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287988.pdf [firstpage_image] =>[orig_patent_app_number] => 039980 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/039980
Semiconductor device manufacturing method, semiconductor device manufacturing apparatus and semiconductor device Mar 16, 1998 Issued
Array ( [id] => 6886578 [patent_doc_number] => 20010019847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-06 [patent_title] => 'METHOD OF FORMING THIN COPPER FILM' [patent_app_type] => new [patent_app_number] => 09/038117 [patent_app_country] => US [patent_app_date] => 1998-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4216 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20010019847.pdf [firstpage_image] =>[orig_patent_app_number] => 09038117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/038117
Method of forming thin copper film and semiconductor device with thin copper film Mar 10, 1998 Issued
Array ( [id] => 4238353 [patent_doc_number] => 06080647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Process to form a trench-free buried contact' [patent_app_type] => 1 [patent_app_number] => 9/034927 [patent_app_country] => US [patent_app_date] => 1998-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2851 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080647.pdf [firstpage_image] =>[orig_patent_app_number] => 034927 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/034927
Process to form a trench-free buried contact Mar 4, 1998 Issued
Array ( [id] => 4107524 [patent_doc_number] => 06057202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Method for manufacturing an inductor with resonant frequency and Q value increased in semiconductor process' [patent_app_type] => 1 [patent_app_number] => 9/034947 [patent_app_country] => US [patent_app_date] => 1998-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 1461 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057202.pdf [firstpage_image] =>[orig_patent_app_number] => 034947 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/034947
Method for manufacturing an inductor with resonant frequency and Q value increased in semiconductor process Mar 4, 1998 Issued
Array ( [id] => 4125031 [patent_doc_number] => 06127237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Etching end point detecting method based on junction current measurement and etching apparatus' [patent_app_type] => 1 [patent_app_number] => 9/034220 [patent_app_country] => US [patent_app_date] => 1998-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 9343 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127237.pdf [firstpage_image] =>[orig_patent_app_number] => 034220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/034220
Etching end point detecting method based on junction current measurement and etching apparatus Mar 3, 1998 Issued
Array ( [id] => 4366815 [patent_doc_number] => 06274489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Manufacturing method of semiconductor apparatus' [patent_app_type] => 1 [patent_app_number] => 9/033490 [patent_app_country] => US [patent_app_date] => 1998-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 8288 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274489.pdf [firstpage_image] =>[orig_patent_app_number] => 033490 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/033490
Manufacturing method of semiconductor apparatus Mar 1, 1998 Issued
Array ( [id] => 4188797 [patent_doc_number] => 06153508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Multi-layer circuit having a via matrix interlayer connection and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/026090 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3810 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153508.pdf [firstpage_image] =>[orig_patent_app_number] => 026090 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026090
Multi-layer circuit having a via matrix interlayer connection and method for fabricating the same Feb 18, 1998 Issued
Array ( [id] => 4185327 [patent_doc_number] => 06093587 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Crystallization of amorphous silicon film using a metal catalyst' [patent_app_type] => 1 [patent_app_number] => 9/026888 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 23 [patent_no_of_words] => 5458 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093587.pdf [firstpage_image] =>[orig_patent_app_number] => 026888 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026888
Crystallization of amorphous silicon film using a metal catalyst Feb 18, 1998 Issued
Array ( [id] => 1424480 [patent_doc_number] => 06503825 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Method for forming multi-layer wiring structure' [patent_app_type] => B1 [patent_app_number] => 09/024250 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 4807 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/503/06503825.pdf [firstpage_image] =>[orig_patent_app_number] => 09024250 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024250
Method for forming multi-layer wiring structure Feb 16, 1998 Issued
Array ( [id] => 4245287 [patent_doc_number] => 06136616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method of forming semiconductor devices using gate electrode dimensions and dopant concentration for controlling drive current strength' [patent_app_type] => 1 [patent_app_number] => 9/022129 [patent_app_country] => US [patent_app_date] => 1998-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2741 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136616.pdf [firstpage_image] =>[orig_patent_app_number] => 022129 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/022129
Method of forming semiconductor devices using gate electrode dimensions and dopant concentration for controlling drive current strength Feb 10, 1998 Issued
Array ( [id] => 4029770 [patent_doc_number] => 05994205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method of separating semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/017238 [patent_app_country] => US [patent_app_date] => 1998-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 6726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994205.pdf [firstpage_image] =>[orig_patent_app_number] => 017238 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/017238
Method of separating semiconductor devices Feb 1, 1998 Issued
Array ( [id] => 4238729 [patent_doc_number] => 06080673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Chemical mechanical polishing methods utilizing pH-adjusted polishing solutions' [patent_app_type] => 1 [patent_app_number] => 9/010329 [patent_app_country] => US [patent_app_date] => 1998-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1861 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080673.pdf [firstpage_image] =>[orig_patent_app_number] => 010329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/010329
Chemical mechanical polishing methods utilizing pH-adjusted polishing solutions Jan 20, 1998 Issued
Array ( [id] => 4087546 [patent_doc_number] => 06133138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method of manufacturing semiconductor device having multilayer interconnection structure' [patent_app_type] => 1 [patent_app_number] => 9/009177 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 44 [patent_no_of_words] => 3160 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133138.pdf [firstpage_image] =>[orig_patent_app_number] => 009177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/009177
Method of manufacturing semiconductor device having multilayer interconnection structure Jan 19, 1998 Issued
Array ( [id] => 1503538 [patent_doc_number] => 06465322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-15 [patent_title] => 'Semiconductor processing methods and structures for determining alignment during semiconductor wafer processing' [patent_app_type] => B2 [patent_app_number] => 09/007673 [patent_app_country] => US [patent_app_date] => 1998-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 4554 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465322.pdf [firstpage_image] =>[orig_patent_app_number] => 09007673 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/007673
Semiconductor processing methods and structures for determining alignment during semiconductor wafer processing Jan 14, 1998 Issued
Array ( [id] => 4232253 [patent_doc_number] => 06117692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Calibrated methods of forming hemispherical grained silicon layers' [patent_app_type] => 1 [patent_app_number] => 9/007879 [patent_app_country] => US [patent_app_date] => 1998-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3422 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117692.pdf [firstpage_image] =>[orig_patent_app_number] => 007879 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/007879
Calibrated methods of forming hemispherical grained silicon layers Jan 13, 1998 Issued
Array ( [id] => 4420330 [patent_doc_number] => 06225190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Process for the separation of at least two elements of a structure in contact with one another by ion implantation' [patent_app_type] => 1 [patent_app_number] => 8/970077 [patent_app_country] => US [patent_app_date] => 1997-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3037 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225190.pdf [firstpage_image] =>[orig_patent_app_number] => 970077 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970077
Process for the separation of at least two elements of a structure in contact with one another by ion implantation Nov 12, 1997 Issued
Array ( [id] => 4366267 [patent_doc_number] => 06274452 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Semiconductor device having multilayer interconnection structure and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/965030 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 5843 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274452.pdf [firstpage_image] =>[orig_patent_app_number] => 965030 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/965030
Semiconductor device having multilayer interconnection structure and method for manufacturing the same Nov 4, 1997 Issued
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