
Kaushikkumar M. Patel
Examiner (ID: 9402, Phone: (571)272-5536 , Office: P/2138 )
| Most Active Art Unit | 2138 |
| Art Unit(s) | 2138, 2186, 2188 |
| Total Applications | 1024 |
| Issued Applications | 814 |
| Pending Applications | 45 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10609766
[patent_doc_number] => 09329796
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-03
[patent_title] => 'Management of memory pages'
[patent_app_type] => utility
[patent_app_number] => 14/972129
[patent_app_country] => US
[patent_app_date] => 2015-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 8180
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 551
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14972129
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/972129 | Management of memory pages | Dec 16, 2015 | Issued |
Array
(
[id] => 12173915
[patent_doc_number] => 09892060
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-13
[patent_title] => 'Identifying stale entries in address translation cache'
[patent_app_type] => utility
[patent_app_number] => 14/956789
[patent_app_country] => US
[patent_app_date] => 2015-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 10044
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14956789
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/956789 | Identifying stale entries in address translation cache | Dec 1, 2015 | Issued |
Array
(
[id] => 12310929
[patent_doc_number] => 09940020
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-04-10
[patent_title] => Memory management method, apparatus, and system
[patent_app_type] => utility
[patent_app_number] => 14/942719
[patent_app_country] => US
[patent_app_date] => 2015-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 24538
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942719
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/942719 | Memory management method, apparatus, and system | Nov 15, 2015 | Issued |
Array
(
[id] => 13029321
[patent_doc_number] => 10037281
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-31
[patent_title] => Method for disk defrag handling in solid state drive caching environment
[patent_app_type] => utility
[patent_app_number] => 14/937840
[patent_app_country] => US
[patent_app_date] => 2015-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 4829
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14937840
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/937840 | Method for disk defrag handling in solid state drive caching environment | Nov 9, 2015 | Issued |
Array
(
[id] => 11606421
[patent_doc_number] => 20170123725
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-04
[patent_title] => 'REDUCING PAGE INVALIDATION BROADCASTS IN VIRTUAL STORAGE MANAGEMENT'
[patent_app_type] => utility
[patent_app_number] => 14/925250
[patent_app_country] => US
[patent_app_date] => 2015-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7354
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14925250
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/925250 | Reducing page invalidation broadcasts in virtual storage management | Oct 27, 2015 | Issued |
Array
(
[id] => 11917199
[patent_doc_number] => 09785384
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-10-10
[patent_title] => 'Semiconductor storage device and method for controlling nonvolatile semiconductor memory'
[patent_app_type] => utility
[patent_app_number] => 14/918062
[patent_app_country] => US
[patent_app_date] => 2015-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 8816
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14918062
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/918062 | Semiconductor storage device and method for controlling nonvolatile semiconductor memory | Oct 19, 2015 | Issued |
Array
(
[id] => 11570447
[patent_doc_number] => 20170109091
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-20
[patent_title] => 'APPARATUSES AND METHODS FOR ARBITRATING A SHARED TERMINAL FOR CALIBRATION OF AN IMPEDANCE TERMINATION'
[patent_app_type] => utility
[patent_app_number] => 14/883454
[patent_app_country] => US
[patent_app_date] => 2015-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 11499
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14883454
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/883454 | Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination | Oct 13, 2015 | Issued |
Array
(
[id] => 13017125
[patent_doc_number] => 10031677
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-07-24
[patent_title] => High-throughput low-latency hybrid memory module
[patent_app_type] => utility
[patent_app_number] => 14/883155
[patent_app_country] => US
[patent_app_date] => 2015-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 13532
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14883155
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/883155 | High-throughput low-latency hybrid memory module | Oct 13, 2015 | Issued |
Array
(
[id] => 12173718
[patent_doc_number] => 09891861
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-13
[patent_title] => 'Off-line affinity-aware parallel zeroing of memory in non-uniform memory access (NUMA) servers'
[patent_app_type] => utility
[patent_app_number] => 14/883402
[patent_app_country] => US
[patent_app_date] => 2015-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10002
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14883402
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/883402 | Off-line affinity-aware parallel zeroing of memory in non-uniform memory access (NUMA) servers | Oct 13, 2015 | Issued |
Array
(
[id] => 13679303
[patent_doc_number] => 20160378388
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-29
[patent_title] => AFFINITY-AWARE PARALLEL ZEROING OF MEMORY FOR INITIALIZATION OF LARGE PAGES IN NON-UNIFORM MEMORY ACCESS (NUMA) SERVERS
[patent_app_type] => utility
[patent_app_number] => 14/883304
[patent_app_country] => US
[patent_app_date] => 2015-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9719
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14883304
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/883304 | Affinity-aware parallel zeroing of memory for initialization of large pages in non-uniform memory access (NUMA) servers | Oct 13, 2015 | Issued |
Array
(
[id] => 11116970
[patent_doc_number] => 20160313944
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-27
[patent_title] => 'Method and System for Limiting Write Command Execution'
[patent_app_type] => utility
[patent_app_number] => 14/883540
[patent_app_country] => US
[patent_app_date] => 2015-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 10980
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14883540
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/883540 | Method and system for limiting write command execution | Oct 13, 2015 | Issued |
Array
(
[id] => 13679321
[patent_doc_number] => 20160378397
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-29
[patent_title] => AFFINITY-AWARE PARALLEL ZEROING OF PAGES IN NON-UNIFORM MEMORY ACCESS (NUMA) SERVERS
[patent_app_type] => utility
[patent_app_number] => 14/883361
[patent_app_country] => US
[patent_app_date] => 2015-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9928
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14883361
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/883361 | Affinity-aware parallel zeroing of pages in non-uniform memory access (NUMA) servers | Oct 13, 2015 | Issued |
Array
(
[id] => 11326863
[patent_doc_number] => 20160357474
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-08
[patent_title] => 'SCHEDULING SCHEME(S) FOR A MULTI-DIE STORAGE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/883496
[patent_app_country] => US
[patent_app_date] => 2015-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 26215
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14883496
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/883496 | Scheduling scheme(s) for a multi-die storage device | Oct 13, 2015 | Issued |
Array
(
[id] => 12108201
[patent_doc_number] => 09864686
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-09
[patent_title] => 'Restriction of validation to active tracks in non-volatile storage during a warmstart recovery'
[patent_app_type] => utility
[patent_app_number] => 14/883382
[patent_app_country] => US
[patent_app_date] => 2015-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7273
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14883382
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/883382 | Restriction of validation to active tracks in non-volatile storage during a warmstart recovery | Oct 13, 2015 | Issued |
Array
(
[id] => 11830721
[patent_doc_number] => 09727463
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-08
[patent_title] => 'Assymetric coherent caching for heterogeneous computing'
[patent_app_type] => utility
[patent_app_number] => 14/882617
[patent_app_country] => US
[patent_app_date] => 2015-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3407
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14882617
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/882617 | Assymetric coherent caching for heterogeneous computing | Oct 13, 2015 | Issued |
Array
(
[id] => 13767547
[patent_doc_number] => 10176117
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-08
[patent_title] => Efficient metadata in a storage system
[patent_app_type] => utility
[patent_app_number] => 15/516265
[patent_app_country] => US
[patent_app_date] => 2015-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3308
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15516265
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/516265 | Efficient metadata in a storage system | Sep 29, 2015 | Issued |
Array
(
[id] => 10493894
[patent_doc_number] => 20150378916
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-31
[patent_title] => 'MITIGATING BUSY TIME IN A HIGH PERFORMANCE CACHE'
[patent_app_type] => utility
[patent_app_number] => 14/847319
[patent_app_country] => US
[patent_app_date] => 2015-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6053
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14847319
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/847319 | Mitigating busy time in a high performance cache | Sep 7, 2015 | Issued |
Array
(
[id] => 10702197
[patent_doc_number] => 20160048344
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-18
[patent_title] => 'DISTRIBUTED CACHING SYSTEMS AND METHODS'
[patent_app_type] => utility
[patent_app_number] => 14/825927
[patent_app_country] => US
[patent_app_date] => 2015-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 7142
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14825927
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/825927 | DISTRIBUTED CACHING SYSTEMS AND METHODS | Aug 12, 2015 | Abandoned |
Array
(
[id] => 11445070
[patent_doc_number] => 20170046090
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-16
[patent_title] => 'WOM CODE EMULATION OF EEPROM-TYPE DEVICES'
[patent_app_type] => utility
[patent_app_number] => 14/826183
[patent_app_country] => US
[patent_app_date] => 2015-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7767
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14826183
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/826183 | WOM code emulation of EEPROM-type devices | Aug 12, 2015 | Issued |
Array
(
[id] => 11882677
[patent_doc_number] => 09753850
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-09-05
[patent_title] => 'On-heap huge slab allocator'
[patent_app_type] => utility
[patent_app_number] => 14/826053
[patent_app_country] => US
[patent_app_date] => 2015-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2429
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14826053
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/826053 | On-heap huge slab allocator | Aug 12, 2015 | Issued |