Search

Kaushikkumar M. Patel

Examiner (ID: 9402, Phone: (571)272-5536 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2138, 2186, 2188
Total Applications
1024
Issued Applications
814
Pending Applications
45
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8935578 [patent_doc_number] => 08495295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Mass storage system and method of operating thereof' [patent_app_type] => utility [patent_app_number] => 12/776708 [patent_app_country] => US [patent_app_date] => 2010-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6447 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12776708 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/776708
Mass storage system and method of operating thereof May 9, 2010 Issued
Array ( [id] => 10901438 [patent_doc_number] => 08924681 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-30 [patent_title] => 'Systems, methods, and computer readable media for an adaptative block allocation mechanism' [patent_app_type] => utility [patent_app_number] => 12/751685 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7169 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12751685 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/751685
Systems, methods, and computer readable media for an adaptative block allocation mechanism Mar 30, 2010 Issued
Array ( [id] => 8060589 [patent_doc_number] => 20110246724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'System and Method for Providing Locale-Based Optimizations In a Transactional Memory' [patent_app_type] => utility [patent_app_number] => 12/750884 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 16480 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20110246724.pdf [firstpage_image] =>[orig_patent_app_number] => 12750884 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/750884
System and method for providing locale-based optimizations in a transactional memory Mar 30, 2010 Issued
Array ( [id] => 6280852 [patent_doc_number] => 20100257327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'MEMORY DEVICE AND SYSTEM INCLUDING A MEMORY DEVICE ELECTRONICALLY CONNECTABLE TO A HOST CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/751438 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 28411 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20100257327.pdf [firstpage_image] =>[orig_patent_app_number] => 12751438 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/751438
Memory device and system including a memory device electronically connectable to a host circuit Mar 30, 2010 Issued
Array ( [id] => 8060641 [patent_doc_number] => 20110246703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'CONSTRAINED CODING TO REDUCE FLOATING GATE COUPLING IN NON-VOLATILE MEMORIES' [patent_app_type] => utility [patent_app_number] => 12/751197 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7177 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20110246703.pdf [firstpage_image] =>[orig_patent_app_number] => 12751197 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/751197
Constrained coding to reduce floating gate coupling in non-volatile memories Mar 30, 2010 Issued
Array ( [id] => 8060595 [patent_doc_number] => 20110246725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'System and Method for Committing Results of a Software Transaction Using a Hardware Transaction' [patent_app_type] => utility [patent_app_number] => 12/750908 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20110246725.pdf [firstpage_image] =>[orig_patent_app_number] => 12750908 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/750908
System and method for committing results of a software transaction using a hardware transaction Mar 30, 2010 Issued
Array ( [id] => 8728303 [patent_doc_number] => 08407445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-26 [patent_title] => 'Systems, methods, and computer readable media for triggering and coordinating pool storage reclamation' [patent_app_type] => utility [patent_app_number] => 12/751665 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5042 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12751665 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/751665
Systems, methods, and computer readable media for triggering and coordinating pool storage reclamation Mar 30, 2010 Issued
Array ( [id] => 8546323 [patent_doc_number] => 08321626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Management of configuration data using persistent memories requiring block-wise erase before rewriting' [patent_app_type] => utility [patent_app_number] => 12/750724 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4969 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12750724 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/750724
Management of configuration data using persistent memories requiring block-wise erase before rewriting Mar 30, 2010 Issued
Array ( [id] => 8449087 [patent_doc_number] => 08291154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Memory device accepting write data and inverted write data from a host circuit' [patent_app_type] => utility [patent_app_number] => 12/750835 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 28328 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12750835 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/750835
Memory device accepting write data and inverted write data from a host circuit Mar 30, 2010 Issued
Array ( [id] => 8060605 [patent_doc_number] => 20110246721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'METHOD AND APPARATUS FOR PROVIDING AUTOMATIC SYNCHRONIZATION APPLIANCE' [patent_app_type] => utility [patent_app_number] => 12/751691 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3895 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20110246721.pdf [firstpage_image] =>[orig_patent_app_number] => 12751691 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/751691
METHOD AND APPARATUS FOR PROVIDING AUTOMATIC SYNCHRONIZATION APPLIANCE Mar 30, 2010 Abandoned
Array ( [id] => 6532761 [patent_doc_number] => 20100262774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'STORAGE CONTROL APPARATUS AND STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/751289 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4896 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20100262774.pdf [firstpage_image] =>[orig_patent_app_number] => 12751289 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/751289
STORAGE CONTROL APPARATUS AND STORAGE SYSTEM Mar 30, 2010 Abandoned
Array ( [id] => 9781263 [patent_doc_number] => 08856485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Storage system and storage control method' [patent_app_type] => utility [patent_app_number] => 12/751566 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6544 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12751566 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/751566
Storage system and storage control method Mar 30, 2010 Issued
Array ( [id] => 4510694 [patent_doc_number] => 07949833 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-24 [patent_title] => 'Transparent level 2 cache controller' [patent_app_type] => utility [patent_app_number] => 12/728583 [patent_app_country] => US [patent_app_date] => 2010-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/949/07949833.pdf [firstpage_image] =>[orig_patent_app_number] => 12728583 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/728583
Transparent level 2 cache controller Mar 21, 2010 Issued
Array ( [id] => 6067467 [patent_doc_number] => 20110202740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-18 [patent_title] => 'Storing secure page table data in secure and non-secure regions of memory' [patent_app_type] => utility [patent_app_number] => 12/656849 [patent_app_country] => US [patent_app_date] => 2010-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7223 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20110202740.pdf [firstpage_image] =>[orig_patent_app_number] => 12656849 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656849
Storing secure page table data in secure and non-secure regions of memory Feb 16, 2010 Abandoned
Array ( [id] => 8472663 [patent_doc_number] => 08301856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Restricting memory areas for an instruction read in dependence upon a hardware mode and a security flag' [patent_app_type] => utility [patent_app_number] => 12/656786 [patent_app_country] => US [patent_app_date] => 2010-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3752 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12656786 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656786
Restricting memory areas for an instruction read in dependence upon a hardware mode and a security flag Feb 15, 2010 Issued
Array ( [id] => 6252841 [patent_doc_number] => 20100138606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'Method for Controlling Non-Volatile Semiconductor Memory System' [patent_app_type] => utility [patent_app_number] => 12/702134 [patent_app_country] => US [patent_app_date] => 2010-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 20889 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20100138606.pdf [firstpage_image] =>[orig_patent_app_number] => 12702134 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/702134
Method for controlling non-volatile semiconductor memory system Feb 7, 2010 Issued
Array ( [id] => 4626746 [patent_doc_number] => 08006057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Memory devices with buffered command address bus' [patent_app_type] => utility [patent_app_number] => 12/697558 [patent_app_country] => US [patent_app_date] => 2010-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5831 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/006/08006057.pdf [firstpage_image] =>[orig_patent_app_number] => 12697558 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/697558
Memory devices with buffered command address bus Jan 31, 2010 Issued
Array ( [id] => 8273094 [patent_doc_number] => 08214615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Control method of device in storage system for virtualization' [patent_app_type] => utility [patent_app_number] => 12/691197 [patent_app_country] => US [patent_app_date] => 2010-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 15297 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12691197 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/691197
Control method of device in storage system for virtualization Jan 20, 2010 Issued
Array ( [id] => 7684112 [patent_doc_number] => 20100122029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'MEMORY CONTROL DEVICE AND METHOD FOR CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/688564 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8330 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20100122029.pdf [firstpage_image] =>[orig_patent_app_number] => 12688564 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/688564
Memory control device and method for controlling the same Jan 14, 2010 Issued
Array ( [id] => 6363371 [patent_doc_number] => 20100250841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'Memory controlling device' [patent_app_type] => utility [patent_app_number] => 12/656045 [patent_app_country] => US [patent_app_date] => 2010-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 23283 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20100250841.pdf [firstpage_image] =>[orig_patent_app_number] => 12656045 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656045
Memory controlling device Jan 13, 2010 Issued
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