Search

Kaushikkumar M. Patel

Examiner (ID: 17612, Phone: (571)272-5536 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2186
Total Applications
1006
Issued Applications
799
Pending Applications
43
Abandoned Applications
178

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18438439 [patent_doc_number] => 20230185734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => PACKET PROCESSING SYSTEM, METHOD AND DEVICE UTILIZING A PORT CLIENT CHAIN [patent_app_type] => utility [patent_app_number] => 18/105700 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105700
Packet processing system, method and device utilizing a port client chain Feb 2, 2023 Issued
Array ( [id] => 20110180 [patent_doc_number] => 12360901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Memory performance during program suspend protocol [patent_app_type] => utility [patent_app_number] => 18/104897 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104897 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104897
Memory performance during program suspend protocol Feb 1, 2023 Issued
Array ( [id] => 18407650 [patent_doc_number] => 20230169003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => Scalable Cache Coherency Protocol [patent_app_type] => utility [patent_app_number] => 18/160575 [patent_app_country] => US [patent_app_date] => 2023-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18987 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18160575 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/160575
Scalable cache coherency protocol Jan 26, 2023 Issued
Array ( [id] => 19566700 [patent_doc_number] => 12141472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Providing communication between storage processors through an interconnect and a set of storage devices [patent_app_type] => utility [patent_app_number] => 18/095687 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9526 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18095687 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/095687
Providing communication between storage processors through an interconnect and a set of storage devices Jan 10, 2023 Issued
Array ( [id] => 18351488 [patent_doc_number] => 20230139599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => STACKED MEMORY AND STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/146996 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146996 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/146996
Stacked memory and storage system Dec 26, 2022 Issued
Array ( [id] => 18325795 [patent_doc_number] => 20230123923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => METHODS AND SYSTEMS FOR DATA RESYNCHRONIZATION IN A REPLICATION ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 18/068774 [patent_app_country] => US [patent_app_date] => 2022-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068774 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/068774
Methods and systems for data resynchronization in a replication environment Dec 19, 2022 Issued
Array ( [id] => 19740072 [patent_doc_number] => 12216907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Method of improving programming operations in 3D NAND systems [patent_app_type] => utility [patent_app_number] => 18/082265 [patent_app_country] => US [patent_app_date] => 2022-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18082265 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/082265
Method of improving programming operations in 3D NAND systems Dec 14, 2022 Issued
Array ( [id] => 19061688 [patent_doc_number] => 11940922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => ISA extension for high-bandwidth memory [patent_app_type] => utility [patent_app_number] => 18/081488 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5045 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18081488 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/081488
ISA extension for high-bandwidth memory Dec 13, 2022 Issued
Array ( [id] => 19911530 [patent_doc_number] => 12287739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Accessing a cache based on an address translation buffer result [patent_app_type] => utility [patent_app_number] => 18/064155 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1266 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064155 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/064155
Accessing a cache based on an address translation buffer result Dec 8, 2022 Issued
Array ( [id] => 18286595 [patent_doc_number] => 20230102067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => REMOVING CORE MEMORY ACCESSES IN HASH TABLE LOOKUPS USING AN ACCELERATOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/076120 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18076120 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/076120
REMOVING CORE MEMORY ACCESSES IN HASH TABLE LOOKUPS USING AN ACCELERATOR DEVICE Dec 5, 2022 Pending
Array ( [id] => 19956397 [patent_doc_number] => 12326811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Fault tolerant systems and methods using shared memory configurations [patent_app_type] => utility [patent_app_number] => 18/072297 [patent_app_country] => US [patent_app_date] => 2022-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2496 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18072297 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/072297
Fault tolerant systems and methods using shared memory configurations Nov 29, 2022 Issued
Array ( [id] => 19144270 [patent_doc_number] => 20240143182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => DATA READING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 17/994013 [patent_app_country] => US [patent_app_date] => 2022-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994013 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/994013
Data reading method, memory storage device, and memory control circuit unit Nov 24, 2022 Issued
Array ( [id] => 18256358 [patent_doc_number] => 20230083397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => Scalable Cache Coherency Protocol [patent_app_type] => utility [patent_app_number] => 18/058105 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18058105 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/058105
Scalable cache coherency protocol Nov 21, 2022 Issued
Array ( [id] => 18360583 [patent_doc_number] => 20230142174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => MEMORY SYSTEM USING HOST MEMORY BUFFER AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/979554 [patent_app_country] => US [patent_app_date] => 2022-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17979554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/979554
Memory system using host memory buffer and operation method thereof Nov 1, 2022 Issued
Array ( [id] => 19566680 [patent_doc_number] => 12141452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Host-write-based autonomous compute storage device system [patent_app_type] => utility [patent_app_number] => 17/969720 [patent_app_country] => US [patent_app_date] => 2022-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 19642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17969720 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/969720
Host-write-based autonomous compute storage device system Oct 19, 2022 Issued
Array ( [id] => 19566680 [patent_doc_number] => 12141452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Host-write-based autonomous compute storage device system [patent_app_type] => utility [patent_app_number] => 17/969720 [patent_app_country] => US [patent_app_date] => 2022-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 19642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17969720 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/969720
Host-write-based autonomous compute storage device system Oct 19, 2022 Issued
Array ( [id] => 19610158 [patent_doc_number] => 12159033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Metadata registers for a memory device [patent_app_type] => utility [patent_app_number] => 18/047493 [patent_app_country] => US [patent_app_date] => 2022-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 12620 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047493 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047493
Metadata registers for a memory device Oct 17, 2022 Issued
Array ( [id] => 18965810 [patent_doc_number] => 11899574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => L2P translation techniques in limited RAM systems to increase random write performance using multiple L2P caches [patent_app_type] => utility [patent_app_number] => 17/965542 [patent_app_country] => US [patent_app_date] => 2022-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17965542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/965542
L2P translation techniques in limited RAM systems to increase random write performance using multiple L2P caches Oct 12, 2022 Issued
Array ( [id] => 18989607 [patent_doc_number] => 20240061576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => HOST RATE ADJUSTMENT USING FREE SPACE VALUES [patent_app_type] => utility [patent_app_number] => 17/961050 [patent_app_country] => US [patent_app_date] => 2022-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961050 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/961050
Host rate adjustment using free space values Oct 5, 2022 Issued
Array ( [id] => 19144596 [patent_doc_number] => 20240143513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => APPARATUS AND METHOD FOR SWITCHING BETWEEN PAGE TABLE TYPES [patent_app_type] => utility [patent_app_number] => 17/958337 [patent_app_country] => US [patent_app_date] => 2022-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 66952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958337 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958337
APPARATUS AND METHOD FOR SWITCHING BETWEEN PAGE TABLE TYPES Sep 30, 2022 Pending
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