Search

Kaveh C. Kianni

Examiner (ID: 13038, Phone: (571)272-2417 , Office: P/2883 )

Most Active Art Unit
2883
Art Unit(s)
2874, 2724, 2624, 2877, 2883
Total Applications
2009
Issued Applications
1632
Pending Applications
101
Abandoned Applications
306

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9809726 [patent_doc_number] => 20150021671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THEREOF' [patent_app_type] => utility [patent_app_number] => 14/354996 [patent_app_country] => US [patent_app_date] => 2012-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8185 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14354996 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/354996
FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THEREOF Oct 4, 2012 Abandoned
Array ( [id] => 10864424 [patent_doc_number] => 08890128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-18 [patent_title] => 'Organic display device' [patent_app_type] => utility [patent_app_number] => 13/703074 [patent_app_country] => US [patent_app_date] => 2012-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3332 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13703074 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/703074
Organic display device Sep 25, 2012 Issued
Array ( [id] => 9710762 [patent_doc_number] => 08835330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Integrated circuit including DRAM and SRAM/logic' [patent_app_type] => utility [patent_app_number] => 13/622755 [patent_app_country] => US [patent_app_date] => 2012-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5208 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13622755 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/622755
Integrated circuit including DRAM and SRAM/logic Sep 18, 2012 Issued
Array ( [id] => 9183798 [patent_doc_number] => 08623730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Method for fabricating silicon-on-insulator transistor with self-aligned borderless source/drain contacts' [patent_app_type] => utility [patent_app_number] => 13/617866 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13617866 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/617866
Method for fabricating silicon-on-insulator transistor with self-aligned borderless source/drain contacts Sep 13, 2012 Issued
Array ( [id] => 8563752 [patent_doc_number] => 20120326323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'HIGH VOLTAGE HIGH PACKAGE PRESSURE SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/604396 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604396 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604396
HIGH VOLTAGE HIGH PACKAGE PRESSURE SEMICONDUCTOR PACKAGE Sep 4, 2012 Abandoned
Array ( [id] => 8520332 [patent_doc_number] => 20120319739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'SEMICONDUCTOR DEVICE SUPPLYING CHARGING CURRENT TO ELEMENT TO BE CHARGED' [patent_app_type] => utility [patent_app_number] => 13/596209 [patent_app_country] => US [patent_app_date] => 2012-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 17539 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13596209 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/596209
Semiconductor device supplying charging current to element to be charged Aug 27, 2012 Issued
Array ( [id] => 8506684 [patent_doc_number] => 20120306092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'CONDUCTIVE PADS DEFINED BY EMBEDDED TRACES' [patent_app_type] => utility [patent_app_number] => 13/589359 [patent_app_country] => US [patent_app_date] => 2012-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9366 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13589359 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/589359
Conductive pads defined by embedded traces Aug 19, 2012 Issued
Array ( [id] => 8192885 [patent_doc_number] => 20120119290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING PROTRUSION TYPE ISOLATION LAYER' [patent_app_type] => utility [patent_app_number] => 13/357999 [patent_app_country] => US [patent_app_date] => 2012-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6592 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20120119290.pdf [firstpage_image] =>[orig_patent_app_number] => 13357999 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/357999
SEMICONDUCTOR DEVICE INCLUDING PROTRUSION TYPE ISOLATION LAYER Jan 24, 2012 Abandoned
Array ( [id] => 8299063 [patent_doc_number] => 20120181632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'SEMICONDUCTOR DEVICE AND ITS MANUFACUTURING METHOD' [patent_app_type] => utility [patent_app_number] => 13/353089 [patent_app_country] => US [patent_app_date] => 2012-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9422 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13353089 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/353089
Semiconductor device and its manufacturing method Jan 17, 2012 Issued
Array ( [id] => 8185413 [patent_doc_number] => 20120115267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'METHOD FOR FABRICATING LIGHT EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/349387 [patent_app_country] => US [patent_app_date] => 2012-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4939 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20120115267.pdf [firstpage_image] =>[orig_patent_app_number] => 13349387 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/349387
Method for fabricating light emitting device Jan 11, 2012 Issued
Array ( [id] => 9978085 [patent_doc_number] => 09024397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-05 [patent_title] => 'Thermally-insulated micro-fabricated atomic clock structure and method of forming the atomic clock structure' [patent_app_type] => utility [patent_app_number] => 13/345688 [patent_app_country] => US [patent_app_date] => 2012-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 41 [patent_no_of_words] => 12041 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13345688 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/345688
Thermally-insulated micro-fabricated atomic clock structure and method of forming the atomic clock structure Jan 6, 2012 Issued
Array ( [id] => 11776185 [patent_doc_number] => 09385137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Semiconductor memory device and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 13/344757 [patent_app_country] => US [patent_app_date] => 2012-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 41 [patent_no_of_words] => 8557 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13344757 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/344757
Semiconductor memory device and method for manufacturing same Jan 5, 2012 Issued
Array ( [id] => 8914007 [patent_doc_number] => 20130175632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'REDUCTION OF CONTACT RESISTANCE AND JUNCTION LEAKAGE' [patent_app_type] => utility [patent_app_number] => 13/345137 [patent_app_country] => US [patent_app_date] => 2012-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6050 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13345137 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/345137
REDUCTION OF CONTACT RESISTANCE AND JUNCTION LEAKAGE Jan 5, 2012 Abandoned
Array ( [id] => 8913994 [patent_doc_number] => 20130175619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'SILICON-ON-INSULATOR TRANSISTOR WITH SELF-ALIGNED BORDERLESS SOURCE/DRAIN CONTACTS' [patent_app_type] => utility [patent_app_number] => 13/345201 [patent_app_country] => US [patent_app_date] => 2012-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13345201 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/345201
SILICON-ON-INSULATOR TRANSISTOR WITH SELF-ALIGNED BORDERLESS SOURCE/DRAIN CONTACTS Jan 5, 2012 Abandoned
Array ( [id] => 8913970 [patent_doc_number] => 20130175595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC' [patent_app_type] => utility [patent_app_number] => 13/344885 [patent_app_country] => US [patent_app_date] => 2012-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5347 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13344885 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/344885
Integrated circuit including DRAM and SRAM/logic Jan 5, 2012 Issued
Array ( [id] => 8914079 [patent_doc_number] => 20130175704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'DISCRETE POWER TRANSISTOR PACKAGE HAVING SOLDERLESS DBC TO LEADFRAME ATTACH' [patent_app_type] => utility [patent_app_number] => 13/344567 [patent_app_country] => US [patent_app_date] => 2012-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4335 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13344567 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/344567
DISCRETE POWER TRANSISTOR PACKAGE HAVING SOLDERLESS DBC TO LEADFRAME ATTACH Jan 4, 2012 Abandoned
Array ( [id] => 10624198 [patent_doc_number] => 09343142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Nanowire floating gate transistor' [patent_app_type] => utility [patent_app_number] => 13/344517 [patent_app_country] => US [patent_app_date] => 2012-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 3638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13344517 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/344517
Nanowire floating gate transistor Jan 4, 2012 Issued
Array ( [id] => 8634728 [patent_doc_number] => 20130026530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'LIGHT EMITTING DEVICE MODULE' [patent_app_type] => utility [patent_app_number] => 13/343141 [patent_app_country] => US [patent_app_date] => 2012-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4863 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13343141 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/343141
Light emitting device module Jan 3, 2012 Issued
Array ( [id] => 10883016 [patent_doc_number] => 08907396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-09 [patent_title] => 'Source/drain zones with a delectric plug over an isolation region between active regions and methods' [patent_app_type] => utility [patent_app_number] => 13/343087 [patent_app_country] => US [patent_app_date] => 2012-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 32 [patent_no_of_words] => 14867 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13343087 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/343087
Source/drain zones with a delectric plug over an isolation region between active regions and methods Jan 3, 2012 Issued
Array ( [id] => 8812017 [patent_doc_number] => 20130113062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'Lens Holder, Method for Manufacturing the Same and Image Capturing Device Thereof' [patent_app_type] => utility [patent_app_number] => 13/342682 [patent_app_country] => US [patent_app_date] => 2012-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3640 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13342682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/342682
Lens Holder, Method for Manufacturing the Same and Image Capturing Device Thereof Jan 2, 2012 Abandoned
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