Kawing Chan

Array ( [id] => 5809456 [patent_doc_number] => 20060095812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Exception tracking' [patent_app_type] => utility [patent_app_number] => 10/932733 [patent_app_country] => US [patent_app_date] => 2004-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095812.pdf [firstpage_image] =>[orig_patent_app_number] => 10932733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7192935 [patent_doc_number] => 20050193155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'Data transfer apparatus and transfer control program' [patent_app_type] => utility [patent_app_number] => 10/928129 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5557 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20050193155.pdf [firstpage_image] =>[orig_patent_app_number] => 10928129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5907682 [patent_doc_number] => 20060048163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Method for routing messages between servers located on the same board' [patent_app_type] => utility [patent_app_number] => 10/928418 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20060048163.pdf [firstpage_image] =>[orig_patent_app_number] => 10928418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5906687 [patent_doc_number] => 20060047880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Memory device with HUB capability' [patent_app_type] => utility [patent_app_number] => 10/928488 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20060047880.pdf [firstpage_image] =>[orig_patent_app_number] => 10928488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5906680 [patent_doc_number] => 20060047876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'System and method for processing system management interrupts in a multiple processor system' [patent_app_type] => utility [patent_app_number] => 10/926666 [patent_app_country] => US [patent_app_date] => 2004-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20060047876.pdf [firstpage_image] =>[orig_patent_app_number] => 10926666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 469218 [patent_doc_number] => 07240137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'System and method for message delivery across a plurality of processors' [patent_app_type] => utility [patent_app_number] => 10/926592 [patent_app_country] => US [patent_app_date] => 2004-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240137.pdf [firstpage_image] =>[orig_patent_app_number] => 10926592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5906683 [patent_doc_number] => 20060047878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'GPE register block' [patent_app_type] => utility [patent_app_number] => 10/926204 [patent_app_country] => US [patent_app_date] => 2004-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6177 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20060047878.pdf [firstpage_image] =>[orig_patent_app_number] => 10926204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 290379 [patent_doc_number] => 07549004 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-16 [patent_title] => 'Split filtering in multilayer systems' [patent_app_type] => utility [patent_app_number] => 10/923272 [patent_app_country] => US [patent_app_date] => 2004-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3707 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/549/07549004.pdf [firstpage_image] =>[orig_patent_app_number] => 10923272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5173574 [patent_doc_number] => 20070074013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Dynamic retention of hardware register content in a computer system' [patent_app_type] => utility [patent_app_number] => 10/569199 [patent_app_country] => US [patent_app_date] => 2004-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2519 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20070074013.pdf [firstpage_image] =>[orig_patent_app_number] => 10569199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7261745 [patent_doc_number] => 20050144331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'On-chip serialized peripheral bus system and operating method thereof' [patent_app_type] => utility [patent_app_number] => 10/913418 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4503 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20050144331.pdf [firstpage_image] =>[orig_patent_app_number] => 10913418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4469810 [patent_doc_number] => 07882293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Interrupt masking control' [patent_app_type] => utility [patent_app_number] => 10/886576 [patent_app_country] => US [patent_app_date] => 2004-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2491 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/882/07882293.pdf [firstpage_image] =>[orig_patent_app_number] => 10886576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 749285 [patent_doc_number] => 07032060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Control chip supporting plurality of buses and control chip set thereof' [patent_app_type] => utility [patent_app_number] => 10/710041 [patent_app_country] => US [patent_app_date] => 2004-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2190 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/032/07032060.pdf [firstpage_image] =>[orig_patent_app_number] => 10710041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7266370 [patent_doc_number] => 20040243750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Security or safety bus system' [patent_app_type] => new [patent_app_number] => 10/854861 [patent_app_country] => US [patent_app_date] => 2004-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3692 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20040243750.pdf [firstpage_image] =>[orig_patent_app_number] => 10854861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5882535 [patent_doc_number] => 20060031618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Single wire and three wire bus interoperability' [patent_app_type] => utility [patent_app_number] => 10/851526 [patent_app_country] => US [patent_app_date] => 2004-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 21789 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20060031618.pdf [firstpage_image] =>[orig_patent_app_number] => 10851526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7240568 [patent_doc_number] => 20050256984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Implementation of a master loopback mode' [patent_app_type] => utility [patent_app_number] => 10/844530 [patent_app_country] => US [patent_app_date] => 2004-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20050256984.pdf [firstpage_image] =>[orig_patent_app_number] => 10844530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7036091 [patent_doc_number] => 20050033868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Multi-bus driver apparatus and method for driving a plurality of buses' [patent_app_type] => utility [patent_app_number] => 10/842522 [patent_app_country] => US [patent_app_date] => 2004-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3145 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20050033868.pdf [firstpage_image] =>[orig_patent_app_number] => 10842522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7185227 [patent_doc_number] => 20050125583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Detecting method for PCI system' [patent_app_type] => utility [patent_app_number] => 10/842521 [patent_app_country] => US [patent_app_date] => 2004-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1881 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20050125583.pdf [firstpage_image] =>[orig_patent_app_number] => 10842521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 598937 [patent_doc_number] => 07444454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Systems and methods for interconnection of multiple FPGA devices' [patent_app_type] => utility [patent_app_number] => 10/843226 [patent_app_country] => US [patent_app_date] => 2004-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8609 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/444/07444454.pdf [firstpage_image] =>[orig_patent_app_number] => 10843226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6927028 [patent_doc_number] => 20050240285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Method and system for rapidly starting up an IEEE 1394 network' [patent_app_type] => utility [patent_app_number] => 10/840685 [patent_app_country] => US [patent_app_date] => 2004-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20050240285.pdf [firstpage_image] =>[orig_patent_app_number] => 10840685 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5036496 [patent_doc_number] => 20070101035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Pc card and pc card control method' [patent_app_type] => utility [patent_app_number] => 10/554398 [patent_app_country] => US [patent_app_date] => 2004-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6465 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20070101035.pdf [firstpage_image] =>[orig_patent_app_number] => 10554398 [rel_patent_id] =>[rel_patent_doc_number] =>)