Search

Kawing Chan

Examiner (ID: 11370, Phone: (571)270-3909 , Office: P/2837 )

Most Active Art Unit
2837
Art Unit(s)
2846, 4147, 2837
Total Applications
913
Issued Applications
626
Pending Applications
74
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 27246 [patent_doc_number] => 07802049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Links having flexible lane allocation' [patent_app_type] => utility [patent_app_number] => 10/284847 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9916 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802049.pdf [firstpage_image] =>[orig_patent_app_number] => 10284847 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/284847
Links having flexible lane allocation Oct 29, 2002 Issued
Array ( [id] => 7603649 [patent_doc_number] => 07117289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Claiming cycles on a processor bus in a system having a PCI to PCI bridge north of a memory controller' [patent_app_type] => utility [patent_app_number] => 10/262204 [patent_app_country] => US [patent_app_date] => 2002-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2092 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/117/07117289.pdf [firstpage_image] =>[orig_patent_app_number] => 10262204 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/262204
Claiming cycles on a processor bus in a system having a PCI to PCI bridge north of a memory controller Sep 29, 2002 Issued
Array ( [id] => 7412143 [patent_doc_number] => 20040024940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Central processing unit card with accelerated graphic port' [patent_app_type] => new [patent_app_number] => 10/065237 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3039 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20040024940.pdf [firstpage_image] =>[orig_patent_app_number] => 10065237 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/065237
Central processing unit card with accelerated graphic port Sep 26, 2002 Abandoned
Array ( [id] => 6722329 [patent_doc_number] => 20030056019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Card terminal and method for operating a card terminal' [patent_app_type] => new [patent_app_number] => 10/240033 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3643 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20030056019.pdf [firstpage_image] =>[orig_patent_app_number] => 10240033 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/240033
Card terminal and method for operating a card terminal Sep 25, 2002 Abandoned
Array ( [id] => 6814964 [patent_doc_number] => 20030074514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Interface card for a media card' [patent_app_type] => new [patent_app_number] => 10/253590 [patent_app_country] => US [patent_app_date] => 2002-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3627 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074514.pdf [firstpage_image] =>[orig_patent_app_number] => 10253590 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/253590
Interface card for a media card Sep 24, 2002 Abandoned
Array ( [id] => 6844479 [patent_doc_number] => 20030149826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Access control device for bus bridge circuit and method for controlling the same' [patent_app_type] => new [patent_app_number] => 10/252419 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10956 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20030149826.pdf [firstpage_image] =>[orig_patent_app_number] => 10252419 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/252419
Access control device for bus bridge circuit and method for controlling the same Sep 23, 2002 Issued
Array ( [id] => 7271340 [patent_doc_number] => 20040059858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Methods and arrangements to enhance a downbound path' [patent_app_type] => new [patent_app_number] => 10/252307 [patent_app_country] => US [patent_app_date] => 2002-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5953 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20040059858.pdf [firstpage_image] =>[orig_patent_app_number] => 10252307 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/252307
Methods and arrangements to enhance a downbound path Sep 22, 2002 Abandoned
Array ( [id] => 6852946 [patent_doc_number] => 20030145149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'External bus controller' [patent_app_type] => new [patent_app_number] => 10/247355 [patent_app_country] => US [patent_app_date] => 2002-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5699 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20030145149.pdf [firstpage_image] =>[orig_patent_app_number] => 10247355 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/247355
External bus controller Sep 19, 2002 Issued
Array ( [id] => 7271342 [patent_doc_number] => 20040059860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Double-interface adaptor for memory cards' [patent_app_type] => new [patent_app_number] => 10/246632 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1022 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20040059860.pdf [firstpage_image] =>[orig_patent_app_number] => 10246632 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246632
Double-interface adaptor for memory cards Sep 18, 2002 Abandoned
Array ( [id] => 7473799 [patent_doc_number] => 20040054828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Methods and apparatus for controlling performance of a communications device' [patent_app_type] => new [patent_app_number] => 10/246067 [patent_app_country] => US [patent_app_date] => 2002-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9965 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20040054828.pdf [firstpage_image] =>[orig_patent_app_number] => 10246067 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246067
Methods and apparatus for controlling performance of a communications device Sep 17, 2002 Issued
Array ( [id] => 7473839 [patent_doc_number] => 20040054839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Method of allocating memory to peripheral component interconnect (PCI) devices' [patent_app_type] => new [patent_app_number] => 10/245229 [patent_app_country] => US [patent_app_date] => 2002-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4228 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20040054839.pdf [firstpage_image] =>[orig_patent_app_number] => 10245229 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/245229
Method of allocating memory Sep 15, 2002 Issued
Array ( [id] => 690621 [patent_doc_number] => 07080184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'ISDN-based bus interface' [patent_app_type] => utility [patent_app_number] => 10/065005 [patent_app_country] => US [patent_app_date] => 2002-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3188 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080184.pdf [firstpage_image] =>[orig_patent_app_number] => 10065005 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/065005
ISDN-based bus interface Sep 8, 2002 Issued
Array ( [id] => 882005 [patent_doc_number] => 07360007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'System including a segmentable, shared bus' [patent_app_type] => utility [patent_app_number] => 10/231644 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3069 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/360/07360007.pdf [firstpage_image] =>[orig_patent_app_number] => 10231644 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/231644
System including a segmentable, shared bus Aug 29, 2002 Issued
Array ( [id] => 626312 [patent_doc_number] => 07139860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'On chip network with independent logical and physical layers' [patent_app_type] => utility [patent_app_number] => 10/207588 [patent_app_country] => US [patent_app_date] => 2002-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 49 [patent_no_of_words] => 22850 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139860.pdf [firstpage_image] =>[orig_patent_app_number] => 10207588 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/207588
On chip network with independent logical and physical layers Jul 28, 2002 Issued
Array ( [id] => 7407233 [patent_doc_number] => 20040019710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Hard drive hot insertion and removal notifications' [patent_app_type] => new [patent_app_number] => 10/206604 [patent_app_country] => US [patent_app_date] => 2002-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1860 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20040019710.pdf [firstpage_image] =>[orig_patent_app_number] => 10206604 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/206604
Hard drive hot insertion and removal notifications Jul 25, 2002 Abandoned
Array ( [id] => 7407306 [patent_doc_number] => 20040019718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Method for receiving user defined frame information structure (FIS) types in a serial-ATA (SATA) system' [patent_app_type] => new [patent_app_number] => 10/205063 [patent_app_country] => US [patent_app_date] => 2002-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2245 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20040019718.pdf [firstpage_image] =>[orig_patent_app_number] => 10205063 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/205063
Method for receiving user defined frame information structure (FIS) types in a serial-ATA (SATA) system Jul 24, 2002 Issued
Array ( [id] => 7407362 [patent_doc_number] => 20040019728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Multiple hardware partitions under one input/output hub' [patent_app_type] => new [patent_app_number] => 10/200247 [patent_app_country] => US [patent_app_date] => 2002-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2474 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20040019728.pdf [firstpage_image] =>[orig_patent_app_number] => 10200247 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/200247
Multiple hardware partitions under one input/output hub Jul 22, 2002 Issued
Array ( [id] => 679863 [patent_doc_number] => 07089338 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-08 [patent_title] => 'Method and apparatus for interrupt signaling in a communication network' [patent_app_type] => utility [patent_app_number] => 10/198418 [patent_app_country] => US [patent_app_date] => 2002-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8882 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/089/07089338.pdf [firstpage_image] =>[orig_patent_app_number] => 10198418 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/198418
Method and apparatus for interrupt signaling in a communication network Jul 16, 2002 Issued
Array ( [id] => 645480 [patent_doc_number] => 07124228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Bus communication architecture, in particular for multicomputing systems' [patent_app_type] => utility [patent_app_number] => 10/192759 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 23272 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124228.pdf [firstpage_image] =>[orig_patent_app_number] => 10192759 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/192759
Bus communication architecture, in particular for multicomputing systems Jul 9, 2002 Issued
Array ( [id] => 7457139 [patent_doc_number] => 20040010650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-15 [patent_title] => 'Configurable multi-port multi-protocol network interface to support packet processing' [patent_app_type] => new [patent_app_number] => 10/190851 [patent_app_country] => US [patent_app_date] => 2002-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4894 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20040010650.pdf [firstpage_image] =>[orig_patent_app_number] => 10190851 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190851
Configurable multi-port multi-protocol network interface to support packet processing Jul 8, 2002 Issued
Menu