Kee M. Tung

Array ( [id] => 1156030 [patent_doc_number] => 06771270 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Graphics memory system that utilizes a variable width, stall-free object builder for coalescing and aligning read data' [patent_app_type] => B1 [patent_app_number] => 09/697655 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3596 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/771/06771270.pdf [firstpage_image] =>[orig_patent_app_number] => 09697655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 735832 [patent_doc_number] => 07038692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-02 [patent_title] => 'Method and apparatus for providing a vertex cache' [patent_app_type] => utility [patent_app_number] => 10/042733 [patent_app_country] => US [patent_app_date] => 2000-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/038/07038692.pdf [firstpage_image] =>[orig_patent_app_number] => 10042733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1060866 [patent_doc_number] => 06853382 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-08 [patent_title] => 'Controller for a memory system having multiple partitions' [patent_app_type] => utility [patent_app_number] => 09/687453 [patent_app_country] => US [patent_app_date] => 2000-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5073 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/853/06853382.pdf [firstpage_image] =>[orig_patent_app_number] => 09687453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1126244 [patent_doc_number] => 06795075 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-21 [patent_title] => 'Graphic processor having multiple geometric operation units and method of processing data thereby' [patent_app_type] => B1 [patent_app_number] => 09/685895 [patent_app_country] => US [patent_app_date] => 2000-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 6252 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795075.pdf [firstpage_image] =>[orig_patent_app_number] => 09685895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1313087 [patent_doc_number] => 06618053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Asynchronous multilevel texture pipeline' [patent_app_type] => B1 [patent_app_number] => 09/684315 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6387 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618053.pdf [firstpage_image] =>[orig_patent_app_number] => 09684315 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1138500 [patent_doc_number] => 06784892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-31 [patent_title] => 'Fully associative texture cache having content addressable memory and method for use thereof' [patent_app_type] => B1 [patent_app_number] => 09/684168 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2827 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784892.pdf [firstpage_image] =>[orig_patent_app_number] => 09684168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7629029 [patent_doc_number] => 06819328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Graphic accelerator with interpolate function' [patent_app_type] => B1 [patent_app_number] => 09/676755 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 31 [patent_no_of_words] => 10270 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/819/06819328.pdf [firstpage_image] =>[orig_patent_app_number] => 09676755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1283403 [patent_doc_number] => 06646647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Display of images from tiled memory' [patent_app_type] => B1 [patent_app_number] => 09/672453 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5529 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/646/06646647.pdf [firstpage_image] =>[orig_patent_app_number] => 09672453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1294687 [patent_doc_number] => 06630936 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Mechanism and method for enabling two graphics controllers to each execute a portion of a single block transform (BLT) in parallel' [patent_app_type] => B1 [patent_app_number] => 09/671237 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5330 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/630/06630936.pdf [firstpage_image] =>[orig_patent_app_number] => 09671237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1347439 [patent_doc_number] => 06590579 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'System for low miss rate replacement of texture cache lines' [patent_app_type] => B1 [patent_app_number] => 09/664988 [patent_app_country] => US [patent_app_date] => 2000-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3298 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/590/06590579.pdf [firstpage_image] =>[orig_patent_app_number] => 09664988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4296127 [patent_doc_number] => 06268875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Deferred shading graphics pipeline processor' [patent_app_type] => 1 [patent_app_number] => 9/632293 [patent_app_country] => US [patent_app_date] => 2000-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 17836 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268875.pdf [firstpage_image] =>[orig_patent_app_number] => 632293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1190597 [patent_doc_number] => 06734860 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Apparatus for providing videodriving capability from various types of DACS' [patent_app_type] => B1 [patent_app_number] => 09/632447 [patent_app_country] => US [patent_app_date] => 2000-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4252 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734860.pdf [firstpage_image] =>[orig_patent_app_number] => 09632447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1339719 [patent_doc_number] => 06597364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Method and system for eliminating frame tears from an output display' [patent_app_type] => B1 [patent_app_number] => 09/632692 [patent_app_country] => US [patent_app_date] => 2000-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3691 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597364.pdf [firstpage_image] =>[orig_patent_app_number] => 09632692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1134476 [patent_doc_number] => 06788302 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Partitioning and load balancing graphical shape data for parallel applications' [patent_app_type] => B1 [patent_app_number] => 09/631764 [patent_app_country] => US [patent_app_date] => 2000-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 13296 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/788/06788302.pdf [firstpage_image] =>[orig_patent_app_number] => 09631764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1219081 [patent_doc_number] => 06707463 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Data normalization technique' [patent_app_type] => B1 [patent_app_number] => 09/611978 [patent_app_country] => US [patent_app_date] => 2000-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 135 [patent_figures_cnt] => 167 [patent_no_of_words] => 68888 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707463.pdf [firstpage_image] =>[orig_patent_app_number] => 09611978 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7624782 [patent_doc_number] => 06724391 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Mechanism for implementing Z-compression transparently' [patent_app_type] => B1 [patent_app_number] => 09/608619 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 9407 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/724/06724391.pdf [firstpage_image] =>[orig_patent_app_number] => 09608619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1569682 [patent_doc_number] => 06377267 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Graphic processing apparatus and method' [patent_app_type] => B1 [patent_app_number] => 09/593496 [patent_app_country] => US [patent_app_date] => 2000-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4310 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377267.pdf [firstpage_image] =>[orig_patent_app_number] => 09593496 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1247242 [patent_doc_number] => 06677952 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Texture download DMA controller synching multiple independently-running rasterizers' [patent_app_type] => B1 [patent_app_number] => 09/591230 [patent_app_country] => US [patent_app_date] => 2000-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 31807 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677952.pdf [firstpage_image] =>[orig_patent_app_number] => 09591230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 722418 [patent_doc_number] => 07050061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-23 [patent_title] => 'Autonomous address translation in graphic subsystem' [patent_app_type] => utility [patent_app_number] => 09/591226 [patent_app_country] => US [patent_app_date] => 2000-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 31118 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/050/07050061.pdf [firstpage_image] =>[orig_patent_app_number] => 09591226 [rel_patent_id] =>[rel_patent_doc_number] =>)