| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 1522957
[patent_doc_number] => 06414688
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-02
[patent_title] => 'Programmable graphics memory method'
[patent_app_type] => B1
[patent_app_number] => 09/239633
[patent_app_country] => US
[patent_app_date] => 1999-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3026
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/414/06414688.pdf
[firstpage_image] =>[orig_patent_app_number] => 09239633
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/239633 | Programmable graphics memory method | Jan 28, 1999 | Issued |
Array
(
[id] => 4283125
[patent_doc_number] => 06323868
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-27
[patent_title] => 'System and method for frame and field memory access in a wide-word memory'
[patent_app_type] => 1
[patent_app_number] => 9/238233
[patent_app_country] => US
[patent_app_date] => 1999-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 7120
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/323/06323868.pdf
[firstpage_image] =>[orig_patent_app_number] => 238233
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/238233 | System and method for frame and field memory access in a wide-word memory | Jan 26, 1999 | Issued |
Array
(
[id] => 4242922
[patent_doc_number] => 06075523
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-13
[patent_title] => 'Reducing power consumption and bus bandwidth requirements in cellular phones and PDAS by using a compressed display cache'
[patent_app_type] => 1
[patent_app_number] => 9/237575
[patent_app_country] => US
[patent_app_date] => 1999-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2991
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/075/06075523.pdf
[firstpage_image] =>[orig_patent_app_number] => 237575
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/237575 | Reducing power consumption and bus bandwidth requirements in cellular phones and PDAS by using a compressed display cache | Jan 25, 1999 | Issued |
Array
(
[id] => 4324391
[patent_doc_number] => 06243099
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Method for interactive viewing full-surround image data and apparatus therefor'
[patent_app_type] => 1
[patent_app_number] => 9/228760
[patent_app_country] => US
[patent_app_date] => 1999-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 21
[patent_no_of_words] => 4489
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/243/06243099.pdf
[firstpage_image] =>[orig_patent_app_number] => 228760
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/228760 | Method for interactive viewing full-surround image data and apparatus therefor | Jan 11, 1999 | Issued |
Array
(
[id] => 4405212
[patent_doc_number] => 06297832
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Method and apparatus for memory access scheduling in a video graphics system'
[patent_app_type] => 1
[patent_app_number] => 9/224692
[patent_app_country] => US
[patent_app_date] => 1999-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5925
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/297/06297832.pdf
[firstpage_image] =>[orig_patent_app_number] => 224692
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/224692 | Method and apparatus for memory access scheduling in a video graphics system | Jan 3, 1999 | Issued |
Array
(
[id] => 4322812
[patent_doc_number] => 06317136
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-13
[patent_title] => 'Motion vector detecting device'
[patent_app_type] => 1
[patent_app_number] => 9/222941
[patent_app_country] => US
[patent_app_date] => 1998-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 2446
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/317/06317136.pdf
[firstpage_image] =>[orig_patent_app_number] => 222941
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/222941 | Motion vector detecting device | Dec 29, 1998 | Issued |
Array
(
[id] => 1551715
[patent_doc_number] => 06346947
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-12
[patent_title] => 'MPEG-decoder and MPEG decoding method with two memory controllers'
[patent_app_type] => B1
[patent_app_number] => 09/222792
[patent_app_country] => US
[patent_app_date] => 1998-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3837
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/346/06346947.pdf
[firstpage_image] =>[orig_patent_app_number] => 09222792
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/222792 | MPEG-decoder and MPEG decoding method with two memory controllers | Dec 29, 1998 | Issued |
Array
(
[id] => 4167894
[patent_doc_number] => 06115054
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Graphics processor emulation system and method with adaptive frame skipping to maintain synchronization between emulation time and real time'
[patent_app_type] => 1
[patent_app_number] => 9/222461
[patent_app_country] => US
[patent_app_date] => 1998-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 17
[patent_no_of_words] => 9612
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/115/06115054.pdf
[firstpage_image] =>[orig_patent_app_number] => 222461
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/222461 | Graphics processor emulation system and method with adaptive frame skipping to maintain synchronization between emulation time and real time | Dec 28, 1998 | Issued |
Array
(
[id] => 1495998
[patent_doc_number] => 06342895
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-29
[patent_title] => 'Apparatus and method for memory allocation'
[patent_app_type] => B1
[patent_app_number] => 09/221982
[patent_app_country] => US
[patent_app_date] => 1998-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 2416
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/342/06342895.pdf
[firstpage_image] =>[orig_patent_app_number] => 09221982
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/221982 | Apparatus and method for memory allocation | Dec 28, 1998 | Issued |
Array
(
[id] => 4279962
[patent_doc_number] => 06307565
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-23
[patent_title] => 'System for dual buffering of asynchronous input to dual port memory for a raster scanned display'
[patent_app_type] => 1
[patent_app_number] => 9/220234
[patent_app_country] => US
[patent_app_date] => 1998-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2582
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/307/06307565.pdf
[firstpage_image] =>[orig_patent_app_number] => 220234
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/220234 | System for dual buffering of asynchronous input to dual port memory for a raster scanned display | Dec 22, 1998 | Issued |
Array
(
[id] => 4243226
[patent_doc_number] => 06075543
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-13
[patent_title] => 'System and method for buffering multiple frames while controlling latency'
[patent_app_type] => 1
[patent_app_number] => 9/217193
[patent_app_country] => US
[patent_app_date] => 1998-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 14
[patent_no_of_words] => 7638
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/075/06075543.pdf
[firstpage_image] =>[orig_patent_app_number] => 217193
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/217193 | System and method for buffering multiple frames while controlling latency | Dec 21, 1998 | Issued |
Array
(
[id] => 1549172
[patent_doc_number] => 06445394
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-03
[patent_title] => 'Serialized mapped memory configuration for a video graphics chip'
[patent_app_type] => B1
[patent_app_number] => 09/212197
[patent_app_country] => US
[patent_app_date] => 1998-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2322
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/445/06445394.pdf
[firstpage_image] =>[orig_patent_app_number] => 09212197
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/212197 | Serialized mapped memory configuration for a video graphics chip | Dec 14, 1998 | Issued |
Array
(
[id] => 1204143
[patent_doc_number] => 06720968
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-13
[patent_title] => 'Video acquisition system including a virtual dual ported memory with adaptive bandwidth allocation'
[patent_app_type] => B1
[patent_app_number] => 09/210636
[patent_app_country] => US
[patent_app_date] => 1998-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4957
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/720/06720968.pdf
[firstpage_image] =>[orig_patent_app_number] => 09210636
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/210636 | Video acquisition system including a virtual dual ported memory with adaptive bandwidth allocation | Dec 10, 1998 | Issued |
Array
(
[id] => 4199638
[patent_doc_number] => 06154223
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Integrated graphics subsystem with message-passing architecture'
[patent_app_type] => 1
[patent_app_number] => 9/207800
[patent_app_country] => US
[patent_app_date] => 1998-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 31876
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/154/06154223.pdf
[firstpage_image] =>[orig_patent_app_number] => 207800
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/207800 | Integrated graphics subsystem with message-passing architecture | Dec 8, 1998 | Issued |
Array
(
[id] => 4270791
[patent_doc_number] => 06259462
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Method and apparatus for texture blending in a video graphics circuit'
[patent_app_type] => 1
[patent_app_number] => 9/208194
[patent_app_country] => US
[patent_app_date] => 1998-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4020
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/259/06259462.pdf
[firstpage_image] =>[orig_patent_app_number] => 208194
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/208194 | Method and apparatus for texture blending in a video graphics circuit | Dec 8, 1998 | Issued |
Array
(
[id] => 4314590
[patent_doc_number] => 06326973
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-04
[patent_title] => 'Method and system for allocating AGP/GART memory from the local AGP memory controller in a highly parallel system architecture (HPSA)'
[patent_app_type] => 1
[patent_app_number] => 9/206677
[patent_app_country] => US
[patent_app_date] => 1998-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 10621
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/326/06326973.pdf
[firstpage_image] =>[orig_patent_app_number] => 206677
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/206677 | Method and system for allocating AGP/GART memory from the local AGP memory controller in a highly parallel system architecture (HPSA) | Dec 6, 1998 | Issued |
Array
(
[id] => 4336170
[patent_doc_number] => 06329997
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-11
[patent_title] => '3-D graphics chip with embedded DRAM buffers'
[patent_app_type] => 1
[patent_app_number] => 9/205505
[patent_app_country] => US
[patent_app_date] => 1998-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4702
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/329/06329997.pdf
[firstpage_image] =>[orig_patent_app_number] => 205505
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/205505 | 3-D graphics chip with embedded DRAM buffers | Dec 3, 1998 | Issued |
| 09/201546 | SYSTEM FOR MANAGING TEXTURE MAPPING DATA IN A COMPUTER GRAPHICS SYSTEM | Nov 29, 1998 | Abandoned |
Array
(
[id] => 4363951
[patent_doc_number] => 06292201
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-18
[patent_title] => 'Integrated circuit device having a core controller, a bus bridge, a graphical controller and a unified memory control unit built therein for use in a computer system'
[patent_app_type] => 1
[patent_app_number] => 9/199478
[patent_app_country] => US
[patent_app_date] => 1998-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 3816
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/292/06292201.pdf
[firstpage_image] =>[orig_patent_app_number] => 199478
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/199478 | Integrated circuit device having a core controller, a bus bridge, a graphical controller and a unified memory control unit built therein for use in a computer system | Nov 24, 1998 | Issued |
Array
(
[id] => 4283098
[patent_doc_number] => 06323866
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-27
[patent_title] => 'Integrated circuit device having a core controller, a bus bridge, a graphical controller and a unified memory control unit built therein for use in a computer system'
[patent_app_type] => 1
[patent_app_number] => 9/199270
[patent_app_country] => US
[patent_app_date] => 1998-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 3902
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/323/06323866.pdf
[firstpage_image] =>[orig_patent_app_number] => 199270
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/199270 | Integrated circuit device having a core controller, a bus bridge, a graphical controller and a unified memory control unit built therein for use in a computer system | Nov 24, 1998 | Issued |