Search

Keith E. Vicary

Examiner (ID: 15210)

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
804
Issued Applications
430
Pending Applications
77
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19771993 [patent_doc_number] => 20250053419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => METHOD AND SYSTEM FOR ACCELERATING RECURRENT NEURAL NETWORK BASED ON CORTEX-M PROCESSOR, AND MEDIUM [patent_app_type] => utility [patent_app_number] => 18/932723 [patent_app_country] => US [patent_app_date] => 2024-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932723 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/932723
METHOD AND SYSTEM FOR ACCELERATING RECURRENT NEURAL NETWORK BASED ON CORTEX-M PROCESSOR, AND MEDIUM Oct 30, 2024 Pending
Array ( [id] => 19747846 [patent_doc_number] => 20250036411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => PADDING IN A STREAM OF MATRIX ELEMENTS [patent_app_type] => utility [patent_app_number] => 18/914395 [patent_app_country] => US [patent_app_date] => 2024-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18914395 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/914395
PADDING IN A STREAM OF MATRIX ELEMENTS Oct 13, 2024 Pending
Array ( [id] => 20629210 [patent_doc_number] => 20260093496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-02 [patent_title] => MACHINE LEARNING FOR BRANCH ANALYSIS [patent_app_type] => utility [patent_app_number] => 18/900449 [patent_app_country] => US [patent_app_date] => 2024-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18900449 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/900449
MACHINE LEARNING FOR BRANCH ANALYSIS Sep 26, 2024 Pending
Array ( [id] => 20616719 [patent_doc_number] => 20260086815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => DEVICE, METHOD AND SYSTEM FOR DETECTING A MISPREDICTION OF AN INSTRUCTION EXECUTION [patent_app_type] => utility [patent_app_number] => 18/898378 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18898378 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/898378
DEVICE, METHOD AND SYSTEM FOR DETECTING A MISPREDICTION OF AN INSTRUCTION EXECUTION Sep 25, 2024 Pending
Array ( [id] => 20520242 [patent_doc_number] => 20260044349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-12 [patent_title] => IDENTIFICATION OF PREDICTION IDENTIFIERS [patent_app_type] => utility [patent_app_number] => 18/829823 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18829823 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/829823
IDENTIFICATION OF PREDICTION IDENTIFIERS Sep 9, 2024 Pending
Array ( [id] => 19644928 [patent_doc_number] => 20240419448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => ARRAY PROCESSOR HAVING AN INSTRUCTION SEQUENCER INCLUDING A PROGRAM STATE CONTROLLER AND LOOP CONTROLLERS [patent_app_type] => utility [patent_app_number] => 18/816208 [patent_app_country] => US [patent_app_date] => 2024-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18816208 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/816208
ARRAY PROCESSOR HAVING AN INSTRUCTION SEQUENCER INCLUDING A PROGRAM STATE CONTROLLER AND LOOP CONTROLLERS Aug 26, 2024 Pending
Array ( [id] => 20543680 [patent_doc_number] => 20260050571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-19 [patent_title] => QUANTIZATION PREDICTION FOR BLOCK DATA [patent_app_type] => utility [patent_app_number] => 18/804214 [patent_app_country] => US [patent_app_date] => 2024-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18804214 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/804214
QUANTIZATION PREDICTION FOR BLOCK DATA Aug 13, 2024 Pending
Array ( [id] => 19848823 [patent_doc_number] => 20250094174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => Coprocessor Prefetcher [patent_app_type] => utility [patent_app_number] => 18/783937 [patent_app_country] => US [patent_app_date] => 2024-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12520 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783937 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783937
Coprocessor Prefetcher Jul 24, 2024 Pending
Array ( [id] => 19725923 [patent_doc_number] => 20250028674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => INSTRUCTION SET ARCHITECTURE FOR IN-MEMORY COMPUTING [patent_app_type] => utility [patent_app_number] => 18/777360 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18777360 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/777360
INSTRUCTION SET ARCHITECTURE FOR IN-MEMORY COMPUTING Jul 17, 2024 Pending
Array ( [id] => 19544991 [patent_doc_number] => 20240362027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => Shared Learning Table for Load Value Prediction and Load Address Prediction [patent_app_type] => utility [patent_app_number] => 18/764611 [patent_app_country] => US [patent_app_date] => 2024-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18764611 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/764611
Shared Learning Table for Load Value Prediction and Load Address Prediction Jul 4, 2024 Pending
Array ( [id] => 20446901 [patent_doc_number] => 20260003623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => Instruction Deltas For Processing-In-Memory Divergence [patent_app_type] => utility [patent_app_number] => 18/757922 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18757922 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/757922
Instruction Deltas For Processing-In-Memory Divergence Jun 27, 2024 Pending
Array ( [id] => 20234279 [patent_doc_number] => 20250291598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => INSTRUCTION FETCH GROUP EXIT POINT PREDICTION USING OFFSET COUNTERS [patent_app_type] => utility [patent_app_number] => 18/759786 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759786 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/759786
INSTRUCTION FETCH GROUP EXIT POINT PREDICTION USING OFFSET COUNTERS Jun 27, 2024 Pending
Array ( [id] => 20446902 [patent_doc_number] => 20260003624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => MULTI-INSTRUCTION FUSION [patent_app_type] => utility [patent_app_number] => 18/754278 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754278 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754278
MULTI-INSTRUCTION FUSION Jun 25, 2024 Pending
Array ( [id] => 20428219 [patent_doc_number] => 20250390309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => TECHNIQUE FOR GENERATING PREDICTIONS OF A TARGET ADDRESS OF BRANCH INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/753513 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753513 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753513
TECHNIQUE FOR GENERATING PREDICTIONS OF A TARGET ADDRESS OF BRANCH INSTRUCTIONS Jun 24, 2024 Pending
Array ( [id] => 20421789 [patent_doc_number] => 20250383874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => PREDICTION CIRCUITRY [patent_app_type] => utility [patent_app_number] => 18/745756 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745756 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/745756
PREDICTION CIRCUITRY Jun 16, 2024 Issued
Array ( [id] => 19481946 [patent_doc_number] => 20240329988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => Load Instruction Fusion [patent_app_type] => utility [patent_app_number] => 18/739070 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739070
Load instruction fusion Jun 9, 2024 Issued
Array ( [id] => 19466338 [patent_doc_number] => 20240320008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => VARIABLE HISTORY LENGTH PERCEPTRON BRANCH PREDICTOR [patent_app_type] => utility [patent_app_number] => 18/680778 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680778 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680778
VARIABLE HISTORY LENGTH PERCEPTRON BRANCH PREDICTOR May 30, 2024 Pending
Array ( [id] => 20395275 [patent_doc_number] => 20250370750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => UNALIGNED LOAD AND STORE IN A CORE [patent_app_type] => utility [patent_app_number] => 18/731006 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3695 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731006 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/731006
UNALIGNED LOAD AND STORE IN A CORE May 30, 2024 Pending
Array ( [id] => 20395280 [patent_doc_number] => 20250370755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => PHYSICAL REGISTER DEALLOCATION IN A PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/680032 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680032 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680032
PHYSICAL REGISTER DEALLOCATION IN A PROCESSING SYSTEM May 30, 2024 Pending
Array ( [id] => 20395241 [patent_doc_number] => 20250370716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => SELF-PROVISIONING AND FLEXIBLE HARDWARE ACCELERATOR ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/678861 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18678861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/678861
SELF-PROVISIONING AND FLEXIBLE HARDWARE ACCELERATOR ARCHITECTURE May 29, 2024 Pending
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