Search

Keith E. Vicary

Examiner (ID: 17556)

Most Active Art Unit
2183
Art Unit(s)
2183, 2182
Total Applications
813
Issued Applications
433
Pending Applications
82
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20487366 [patent_doc_number] => 20260023565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => ADAPTIVE MEMORY ADDRESS COMPUTATION BASED ON TENSOR DIMENSIONS [patent_app_type] => utility [patent_app_number] => 19/212655 [patent_app_country] => US [patent_app_date] => 2025-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19212655 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/212655
ADAPTIVE MEMORY ADDRESS COMPUTATION BASED ON TENSOR DIMENSIONS May 18, 2025 Pending
Array ( [id] => 20616881 [patent_doc_number] => 20260086978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => METHOD OF NOTIFYING A PROCESS OR PROGRAMMABLE ATOMIC OPERATION TRAPS [patent_app_type] => utility [patent_app_number] => 19/198833 [patent_app_country] => US [patent_app_date] => 2025-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19198833 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/198833
METHOD OF NOTIFYING A PROCESS OR PROGRAMMABLE ATOMIC OPERATION TRAPS May 4, 2025 Pending
Array ( [id] => 20087220 [patent_doc_number] => 20250217156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => PIPELINE PROTECTION FOR CPUS WITH SAVE AND RESTORE OF INTERMEDIATE RESULTS [patent_app_type] => utility [patent_app_number] => 19/049097 [patent_app_country] => US [patent_app_date] => 2025-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19049097 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/049097
PIPELINE PROTECTION FOR CPUS WITH SAVE AND RESTORE OF INTERMEDIATE RESULTS Feb 9, 2025 Pending
Array ( [id] => 20009543 [patent_doc_number] => 20250147765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => EXIT HISTORY BASED BRANCH PREDICTION [patent_app_type] => utility [patent_app_number] => 19/016487 [patent_app_country] => US [patent_app_date] => 2025-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19016487 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/016487
EXIT HISTORY BASED BRANCH PREDICTION Jan 9, 2025 Pending
Array ( [id] => 20034931 [patent_doc_number] => 20250173153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => PROCESSOR WITH INSTRUCTION CONCATENATION [patent_app_type] => utility [patent_app_number] => 18/958042 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18958042 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/958042
PROCESSOR WITH INSTRUCTION CONCATENATION Nov 24, 2024 Pending
Array ( [id] => 20601707 [patent_doc_number] => 20260079716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => Load Gathering Techniques [patent_app_type] => utility [patent_app_number] => 18/950951 [patent_app_country] => US [patent_app_date] => 2024-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18950951 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/950951
Load Gathering Techniques Nov 17, 2024 Pending
Array ( [id] => 19771993 [patent_doc_number] => 20250053419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => METHOD AND SYSTEM FOR ACCELERATING RECURRENT NEURAL NETWORK BASED ON CORTEX-M PROCESSOR, AND MEDIUM [patent_app_type] => utility [patent_app_number] => 18/932723 [patent_app_country] => US [patent_app_date] => 2024-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932723 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/932723
METHOD AND SYSTEM FOR ACCELERATING RECURRENT NEURAL NETWORK BASED ON CORTEX-M PROCESSOR, AND MEDIUM Oct 30, 2024 Pending
Array ( [id] => 19747846 [patent_doc_number] => 20250036411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => PADDING IN A STREAM OF MATRIX ELEMENTS [patent_app_type] => utility [patent_app_number] => 18/914395 [patent_app_country] => US [patent_app_date] => 2024-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18914395 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/914395
PADDING IN A STREAM OF MATRIX ELEMENTS Oct 13, 2024 Pending
Array ( [id] => 20629210 [patent_doc_number] => 20260093496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-02 [patent_title] => MACHINE LEARNING FOR BRANCH ANALYSIS [patent_app_type] => utility [patent_app_number] => 18/900449 [patent_app_country] => US [patent_app_date] => 2024-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18900449 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/900449
MACHINE LEARNING FOR BRANCH ANALYSIS Sep 26, 2024 Pending
Array ( [id] => 20745551 [patent_doc_number] => 12645463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Device, method and system for providing branch information to an instruction fetch unit based on a detection of a fall-through event wherein multiple fetched instructions comprise a branch instruction [patent_app_type] => utility [patent_app_number] => 18/898378 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 11483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18898378 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/898378
Device, method and system for providing branch information to an instruction fetch unit based on a detection of a fall-through event wherein multiple fetched instructions comprise a branch instruction Sep 25, 2024 Issued
Array ( [id] => 20520242 [patent_doc_number] => 20260044349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-12 [patent_title] => IDENTIFICATION OF PREDICTION IDENTIFIERS [patent_app_type] => utility [patent_app_number] => 18/829823 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18829823 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/829823
IDENTIFICATION OF PREDICTION IDENTIFIERS Sep 9, 2024 Pending
Array ( [id] => 19644928 [patent_doc_number] => 20240419448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => ARRAY PROCESSOR HAVING AN INSTRUCTION SEQUENCER INCLUDING A PROGRAM STATE CONTROLLER AND LOOP CONTROLLERS [patent_app_type] => utility [patent_app_number] => 18/816208 [patent_app_country] => US [patent_app_date] => 2024-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18816208 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/816208
ARRAY PROCESSOR HAVING AN INSTRUCTION SEQUENCER INCLUDING A PROGRAM STATE CONTROLLER AND LOOP CONTROLLERS Aug 26, 2024 Pending
Array ( [id] => 20556960 [patent_doc_number] => 20260056745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-26 [patent_title] => ENERGY-EFFICIENT INDIRECT PREFETCHER [patent_app_type] => utility [patent_app_number] => 18/812889 [patent_app_country] => US [patent_app_date] => 2024-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18812889 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/812889
ENERGY-EFFICIENT INDIRECT PREFETCHER Aug 21, 2024 Pending
Array ( [id] => 20543680 [patent_doc_number] => 20260050571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-19 [patent_title] => QUANTIZATION PREDICTION FOR BLOCK DATA [patent_app_type] => utility [patent_app_number] => 18/804214 [patent_app_country] => US [patent_app_date] => 2024-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18804214 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/804214
QUANTIZATION PREDICTION FOR BLOCK DATA Aug 13, 2024 Pending
Array ( [id] => 20513229 [patent_doc_number] => 20260037330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => PROCESSING DATA USING ACCELERATORS IN A SYSTEM ON A CHIP [patent_app_type] => utility [patent_app_number] => 18/789957 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789957 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789957
PROCESSING DATA USING ACCELERATORS IN A SYSTEM ON A CHIP Jul 30, 2024 Pending
Array ( [id] => 20773357 [patent_doc_number] => 12657031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Coprocessor prefetcher [patent_app_type] => utility [patent_app_number] => 18/783937 [patent_app_country] => US [patent_app_date] => 2024-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783937 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783937
Coprocessor prefetcher Jul 24, 2024 Issued
Array ( [id] => 19725923 [patent_doc_number] => 20250028674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => INSTRUCTION SET ARCHITECTURE FOR IN-MEMORY COMPUTING [patent_app_type] => utility [patent_app_number] => 18/777360 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18777360 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/777360
INSTRUCTION SET ARCHITECTURE FOR IN-MEMORY COMPUTING Jul 17, 2024 Pending
Array ( [id] => 19544991 [patent_doc_number] => 20240362027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => Shared Learning Table for Load Value Prediction and Load Address Prediction [patent_app_type] => utility [patent_app_number] => 18/764611 [patent_app_country] => US [patent_app_date] => 2024-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18764611 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/764611
Shared Learning Table for Load Value Prediction and Load Address Prediction Jul 4, 2024 Pending
Array ( [id] => 20234279 [patent_doc_number] => 20250291598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => INSTRUCTION FETCH GROUP EXIT POINT PREDICTION USING OFFSET COUNTERS [patent_app_type] => utility [patent_app_number] => 18/759786 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759786 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/759786
INSTRUCTION FETCH GROUP EXIT POINT PREDICTION USING OFFSET COUNTERS Jun 27, 2024 Pending
Array ( [id] => 20446901 [patent_doc_number] => 20260003623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => Instruction Deltas For Processing-In-Memory Divergence [patent_app_type] => utility [patent_app_number] => 18/757922 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18757922 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/757922
Instruction Deltas For Processing-In-Memory Divergence Jun 27, 2024 Pending
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