Search

Keith E. Vicary

Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
798
Issued Applications
429
Pending Applications
76
Abandoned Applications
310

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16910340 [patent_doc_number] => 11042379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Apparatus and method for providing decoded instructions from a decoded instruction cache [patent_app_type] => utility [patent_app_number] => 16/575659 [patent_app_country] => US [patent_app_date] => 2019-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9323 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16575659 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/575659
Apparatus and method for providing decoded instructions from a decoded instruction cache Sep 18, 2019 Issued
Array ( [id] => 15215069 [patent_doc_number] => 20190370221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => CONDITIONAL OPERATION IN AN INTERNAL PROCESSOR OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/545907 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545907 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/545907
Conditional operation in an internal processor of a memory device Aug 19, 2019 Issued
Array ( [id] => 16833919 [patent_doc_number] => 11010170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Arithmetic processing apparatus which replaces values for future branch prediction upon wrong branch prediction [patent_app_type] => utility [patent_app_number] => 16/536354 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11149 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16536354 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/536354
Arithmetic processing apparatus which replaces values for future branch prediction upon wrong branch prediction Aug 8, 2019 Issued
Array ( [id] => 16833950 [patent_doc_number] => 11010202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Distributed physical processing of matrix sum operation [patent_app_type] => utility [patent_app_number] => 16/533588 [patent_app_country] => US [patent_app_date] => 2019-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16533588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/533588
Distributed physical processing of matrix sum operation Aug 5, 2019 Issued
Array ( [id] => 16623471 [patent_doc_number] => 20210042124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => SHARING INSTRUCTION ENCODING SPACE [patent_app_type] => utility [patent_app_number] => 16/531295 [patent_app_country] => US [patent_app_date] => 2019-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16531295 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/531295
Sharing instruction encoding space between a coprocessor and auxiliary execution circuitry Aug 4, 2019 Issued
Array ( [id] => 17325291 [patent_doc_number] => 11216303 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-04 [patent_title] => Integrated task registration and execution system [patent_app_type] => utility [patent_app_number] => 16/524577 [patent_app_country] => US [patent_app_date] => 2019-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16524577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/524577
Integrated task registration and execution system Jul 28, 2019 Issued
Array ( [id] => 15500585 [patent_doc_number] => 20200050481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => Computing Method Applied to Artificial Intelligence Chip, and Artificial Intelligence Chip [patent_app_type] => utility [patent_app_number] => 16/506099 [patent_app_country] => US [patent_app_date] => 2019-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16506099 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/506099
Computing Method Applied to Artificial Intelligence Chip, and Artificial Intelligence Chip Jul 8, 2019 Abandoned
Array ( [id] => 18079609 [patent_doc_number] => 20220405221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => SYSTEM AND ARCHITECTURE OF PURE FUNCTIONAL NEURAL NETWORK ACCELERATOR [patent_app_type] => utility [patent_app_number] => 17/623329 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17623329 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/623329
System and architecture of pure functional neural network accelerator Jul 2, 2019 Issued
Array ( [id] => 15500523 [patent_doc_number] => 20200050450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => Method and Apparatus for Executing Instruction [patent_app_type] => utility [patent_app_number] => 16/458381 [patent_app_country] => US [patent_app_date] => 2019-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458381 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458381
Method and apparatus for executing instructions including a blocking instruction generated in response to determining that there is data dependence between instructions Jun 30, 2019 Issued
Array ( [id] => 16543283 [patent_doc_number] => 20200409698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => APPARATUS AND METHOD FOR OPERATING SYSTEM NOTIFICATION OF INTER-CORE WORK OFFLOAD [patent_app_type] => utility [patent_app_number] => 16/458046 [patent_app_country] => US [patent_app_date] => 2019-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458046 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458046
APPARATUS AND METHOD FOR OPERATING SYSTEM NOTIFICATION OF INTER-CORE WORK OFFLOAD Jun 28, 2019 Abandoned
Array ( [id] => 16543317 [patent_doc_number] => 20200409732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => SHARING MULTIMEDIA PHYSICAL FUNCTIONS IN A VIRTUALIZED ENVIRONMENT ON A PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 16/453664 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453664 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453664
SHARING MULTIMEDIA PHYSICAL FUNCTIONS IN A VIRTUALIZED ENVIRONMENT ON A PROCESSING UNIT Jun 25, 2019 Abandoned
Array ( [id] => 18781180 [patent_doc_number] => 11822923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-11-21 [patent_title] => Performing store-to-load forwarding of a return address for a return instruction [patent_app_type] => utility [patent_app_number] => 16/451783 [patent_app_country] => US [patent_app_date] => 2019-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16451783 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/451783
Performing store-to-load forwarding of a return address for a return instruction Jun 24, 2019 Issued
Array ( [id] => 16527332 [patent_doc_number] => 20200401412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => HARDWARE SUPPORT FOR DUAL-MEMORY ATOMIC OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/450300 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16450300 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/450300
HARDWARE SUPPORT FOR DUAL-MEMORY ATOMIC OPERATIONS Jun 23, 2019 Abandoned
Array ( [id] => 17636793 [patent_doc_number] => 11347517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Reduced precision based programmable and SIMD dataflow architecture [patent_app_type] => utility [patent_app_number] => 16/447588 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16447588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/447588
Reduced precision based programmable and SIMD dataflow architecture Jun 19, 2019 Issued
Array ( [id] => 17039222 [patent_doc_number] => 20210255858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => COMPUTATION DEVICE [patent_app_type] => utility [patent_app_number] => 16/973961 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16973961 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/973961
COMPUTATION DEVICE Jun 18, 2019 Abandoned
Array ( [id] => 16514786 [patent_doc_number] => 20200394044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => METHOD AND APPARATUS FOR CREATING SHARED PIPELINES FOR DATA PROCESSING [patent_app_type] => utility [patent_app_number] => 16/441211 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441211 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441211
Method and apparatus for updating pipeline operations for data processing Jun 13, 2019 Issued
Array ( [id] => 16470256 [patent_doc_number] => 20200371793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => VECTOR STORE USING BIT-REVERSED ORDER [patent_app_type] => utility [patent_app_number] => 16/422602 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422602 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/422602
VECTOR STORE USING BIT-REVERSED ORDER May 23, 2019 Abandoned
Array ( [id] => 16470247 [patent_doc_number] => 20200371784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => VECTOR FLOATING-POINT SCALE [patent_app_type] => utility [patent_app_number] => 16/422754 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422754 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/422754
VECTOR FLOATING-POINT SCALE May 23, 2019 Pending
Array ( [id] => 17180088 [patent_doc_number] => 11157330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Barrier-free atomic transfer of multiword data [patent_app_type] => utility [patent_app_number] => 16/412995 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412995 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/412995
Barrier-free atomic transfer of multiword data May 14, 2019 Issued
Array ( [id] => 16431419 [patent_doc_number] => 10831501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Managing an issue queue for fused instructions and paired instructions in a microprocessor [patent_app_type] => utility [patent_app_number] => 16/408445 [patent_app_country] => US [patent_app_date] => 2019-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7283 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408445 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/408445
Managing an issue queue for fused instructions and paired instructions in a microprocessor May 8, 2019 Issued
Menu