Search

Keith E. Vicary

Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
798
Issued Applications
429
Pending Applications
76
Abandoned Applications
310

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16439045 [patent_doc_number] => 20200356371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => REUSING AN OPERAND IN AN INSTRUCTION SET ARCHITECTURE (ISA) [patent_app_type] => utility [patent_app_number] => 16/406839 [patent_app_country] => US [patent_app_date] => 2019-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16406839 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/406839
Reusing an operand received from a first-in-first-out (FIFO) buffer according to an operand specifier value specified in a predefined field of an instruction May 7, 2019 Issued
Array ( [id] => 16439046 [patent_doc_number] => 20200356372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => EARLY INSTRUCTION EXECUTION WITH VALUE PREDICTION AND LOCAL REGISTER FILE [patent_app_type] => utility [patent_app_number] => 16/406666 [patent_app_country] => US [patent_app_date] => 2019-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16406666 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/406666
EARLY INSTRUCTION EXECUTION WITH VALUE PREDICTION AND LOCAL REGISTER FILE May 7, 2019 Abandoned
Array ( [id] => 17180044 [patent_doc_number] => 11157286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Non-cached loads and stores in a system having a multi-threaded, self-scheduling processor [patent_app_type] => utility [patent_app_number] => 16/399727 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 25188 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399727 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399727
Non-cached loads and stores in a system having a multi-threaded, self-scheduling processor Apr 29, 2019 Issued
Array ( [id] => 14997625 [patent_doc_number] => 20190317770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => SYSTEMS AND METHODS FOR STREAM-DATAFLOW ACCELERATION [patent_app_type] => utility [patent_app_number] => 16/384819 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384819 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/384819
Systems and methods for stream-dataflow acceleration wherein a delay is implemented so as to equalize arrival times of data packets at a destination functional unit Apr 14, 2019 Issued
Array ( [id] => 17031438 [patent_doc_number] => 11093249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Methods for partially preserving a branch predictor state [patent_app_type] => utility [patent_app_number] => 16/292003 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16292003 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/292003
Methods for partially preserving a branch predictor state Mar 3, 2019 Issued
Array ( [id] => 19905769 [patent_doc_number] => 12282777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Programmable control of micro-operations cache resources of a processor [patent_app_type] => utility [patent_app_number] => 17/429467 [patent_app_country] => US [patent_app_date] => 2019-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 33 [patent_no_of_words] => 21206 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17429467 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/429467
Programmable control of micro-operations cache resources of a processor Feb 12, 2019 Issued
Array ( [id] => 18104180 [patent_doc_number] => 11544066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Branch target buffer arrangement with preferential storage for unconditional branch instructions [patent_app_type] => utility [patent_app_number] => 16/971419 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 19705 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16971419 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/971419
Branch target buffer arrangement with preferential storage for unconditional branch instructions Feb 10, 2019 Issued
Array ( [id] => 15578011 [patent_doc_number] => 10579386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Microprocessor for gating a load operation based on entries of a prediction table [patent_app_type] => utility [patent_app_number] => 16/217628 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 13064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16217628 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/217628
Microprocessor for gating a load operation based on entries of a prediction table Dec 11, 2018 Issued
Array ( [id] => 17031440 [patent_doc_number] => 11093251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network [patent_app_type] => utility [patent_app_number] => 16/176434 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 48 [patent_no_of_words] => 60716 [patent_no_of_claims] => 136 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16176434 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/176434
System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network Oct 30, 2018 Issued
Array ( [id] => 18330723 [patent_doc_number] => 11635965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Apparatuses and methods for speculative execution side channel mitigation [patent_app_type] => utility [patent_app_number] => 16/177028 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 35 [patent_no_of_words] => 37802 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177028 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177028
Apparatuses and methods for speculative execution side channel mitigation Oct 30, 2018 Issued
Array ( [id] => 15836785 [patent_doc_number] => 20200133675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => APPARATUS AND METHOD OF MANAGING PREDICTION MECHANISMS USED WHEN FETCHING INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/170383 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16170383 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/170383
Apparatus and method for maintaining prediction performance metrics for prediction components for each of a plurality of execution regions and implementing a prediction adjustment action based thereon Oct 24, 2018 Issued
Array ( [id] => 14161853 [patent_doc_number] => 20190108029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK [patent_app_type] => utility [patent_app_number] => 16/145156 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145156 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/145156
SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK Sep 26, 2018 Abandoned
Array ( [id] => 17031437 [patent_doc_number] => 11093248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Prefetch queue allocation protection bubble in a processor [patent_app_type] => utility [patent_app_number] => 16/125974 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16125974 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/125974
Prefetch queue allocation protection bubble in a processor Sep 9, 2018 Issued
Array ( [id] => 16787971 [patent_doc_number] => 10990404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Apparatus and method for performing branch prediction using loop minimum iteration prediction [patent_app_type] => utility [patent_app_number] => 16/100344 [patent_app_country] => US [patent_app_date] => 2018-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9922 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16100344 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/100344
Apparatus and method for performing branch prediction using loop minimum iteration prediction Aug 9, 2018 Issued
Array ( [id] => 13782755 [patent_doc_number] => 20190004916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTWARE AT CODE REGION GRANULARITY [patent_app_type] => utility [patent_app_number] => 16/026870 [patent_app_country] => US [patent_app_date] => 2018-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16026870 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/026870
PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTWARE AT CODE REGION GRANULARITY Jul 2, 2018 Abandoned
Array ( [id] => 17817195 [patent_doc_number] => 11422806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Parallelized processing of elements of a first vector and a second vector using cyclical transmission of vector elements between processors [patent_app_type] => utility [patent_app_number] => 15/975406 [patent_app_country] => US [patent_app_date] => 2018-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3221 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15975406 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/975406
Parallelized processing of elements of a first vector and a second vector using cyclical transmission of vector elements between processors May 8, 2018 Issued
Array ( [id] => 16240571 [patent_doc_number] => 20200257805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => METHOD FOR EXECUTING A MACHINE CODE OF A SECURE FUNCTION [patent_app_type] => utility [patent_app_number] => 16/603786 [patent_app_country] => US [patent_app_date] => 2018-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 386 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603786 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/603786
Method for executing a machine code formed from blocks having instructions to be protected, each instruction associated with a construction instruction to modify a signature of the block Mar 19, 2018 Issued
Array ( [id] => 16307518 [patent_doc_number] => 10776312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Shared memory access for a reconfigurable parallel processor with a plurality of chained memory ports [patent_app_type] => utility [patent_app_number] => 15/919752 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 35 [patent_no_of_words] => 19541 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919752 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/919752
Shared memory access for a reconfigurable parallel processor with a plurality of chained memory ports Mar 12, 2018 Issued
Array ( [id] => 16217325 [patent_doc_number] => 10733139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Private memory access for a reconfigurable parallel processor using a plurality of chained memory ports [patent_app_type] => utility [patent_app_number] => 15/919727 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 35 [patent_no_of_words] => 19835 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919727 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/919727
Private memory access for a reconfigurable parallel processor using a plurality of chained memory ports Mar 12, 2018 Issued
Array ( [id] => 16307517 [patent_doc_number] => 10776311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Circular reconfiguration for a reconfigurable parallel processor using a plurality of chained memory ports [patent_app_type] => utility [patent_app_number] => 15/919709 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 35 [patent_no_of_words] => 20025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919709 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/919709
Circular reconfiguration for a reconfigurable parallel processor using a plurality of chained memory ports Mar 12, 2018 Issued
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