Search

Keith E. Vicary

Examiner (ID: 17556)

Most Active Art Unit
2183
Art Unit(s)
2183, 2182
Total Applications
813
Issued Applications
433
Pending Applications
82
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19905769 [patent_doc_number] => 12282777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Programmable control of micro-operations cache resources of a processor [patent_app_type] => utility [patent_app_number] => 17/429467 [patent_app_country] => US [patent_app_date] => 2019-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 33 [patent_no_of_words] => 21206 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17429467 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/429467
Programmable control of micro-operations cache resources of a processor Feb 12, 2019 Issued
Array ( [id] => 18104180 [patent_doc_number] => 11544066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Branch target buffer arrangement with preferential storage for unconditional branch instructions [patent_app_type] => utility [patent_app_number] => 16/971419 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 19705 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16971419 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/971419
Branch target buffer arrangement with preferential storage for unconditional branch instructions Feb 10, 2019 Issued
Array ( [id] => 15578011 [patent_doc_number] => 10579386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Microprocessor for gating a load operation based on entries of a prediction table [patent_app_type] => utility [patent_app_number] => 16/217628 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 13064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16217628 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/217628
Microprocessor for gating a load operation based on entries of a prediction table Dec 11, 2018 Issued
Array ( [id] => 18330723 [patent_doc_number] => 11635965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Apparatuses and methods for speculative execution side channel mitigation [patent_app_type] => utility [patent_app_number] => 16/177028 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 35 [patent_no_of_words] => 37802 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177028 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177028
Apparatuses and methods for speculative execution side channel mitigation Oct 30, 2018 Issued
Array ( [id] => 17031440 [patent_doc_number] => 11093251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network [patent_app_type] => utility [patent_app_number] => 16/176434 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 48 [patent_no_of_words] => 60716 [patent_no_of_claims] => 136 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16176434 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/176434
System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network Oct 30, 2018 Issued
Array ( [id] => 15836785 [patent_doc_number] => 20200133675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => APPARATUS AND METHOD OF MANAGING PREDICTION MECHANISMS USED WHEN FETCHING INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/170383 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16170383 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/170383
Apparatus and method for maintaining prediction performance metrics for prediction components for each of a plurality of execution regions and implementing a prediction adjustment action based thereon Oct 24, 2018 Issued
Array ( [id] => 14161853 [patent_doc_number] => 20190108029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK [patent_app_type] => utility [patent_app_number] => 16/145156 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145156 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/145156
SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK Sep 26, 2018 Abandoned
Array ( [id] => 17031437 [patent_doc_number] => 11093248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Prefetch queue allocation protection bubble in a processor [patent_app_type] => utility [patent_app_number] => 16/125974 [patent_app_country] => US [patent_app_date] => 2018-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16125974 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/125974
Prefetch queue allocation protection bubble in a processor Sep 9, 2018 Issued
Array ( [id] => 16787971 [patent_doc_number] => 10990404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Apparatus and method for performing branch prediction using loop minimum iteration prediction [patent_app_type] => utility [patent_app_number] => 16/100344 [patent_app_country] => US [patent_app_date] => 2018-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9922 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16100344 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/100344
Apparatus and method for performing branch prediction using loop minimum iteration prediction Aug 9, 2018 Issued
Array ( [id] => 13782755 [patent_doc_number] => 20190004916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTWARE AT CODE REGION GRANULARITY [patent_app_type] => utility [patent_app_number] => 16/026870 [patent_app_country] => US [patent_app_date] => 2018-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16026870 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/026870
PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTWARE AT CODE REGION GRANULARITY Jul 2, 2018 Abandoned
Array ( [id] => 17817195 [patent_doc_number] => 11422806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Parallelized processing of elements of a first vector and a second vector using cyclical transmission of vector elements between processors [patent_app_type] => utility [patent_app_number] => 15/975406 [patent_app_country] => US [patent_app_date] => 2018-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3221 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15975406 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/975406
Parallelized processing of elements of a first vector and a second vector using cyclical transmission of vector elements between processors May 8, 2018 Issued
Array ( [id] => 16240571 [patent_doc_number] => 20200257805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => METHOD FOR EXECUTING A MACHINE CODE OF A SECURE FUNCTION [patent_app_type] => utility [patent_app_number] => 16/603786 [patent_app_country] => US [patent_app_date] => 2018-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12541 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 386 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603786 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/603786
Method for executing a machine code formed from blocks having instructions to be protected, each instruction associated with a construction instruction to modify a signature of the block Mar 19, 2018 Issued
Array ( [id] => 16307516 [patent_doc_number] => 10776310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Reconfigurable parallel processor with a plurality of chained memory ports [patent_app_type] => utility [patent_app_number] => 15/919681 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 35 [patent_no_of_words] => 21840 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919681 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/919681
Reconfigurable parallel processor with a plurality of chained memory ports Mar 12, 2018 Issued
Array ( [id] => 16706427 [patent_doc_number] => 10956360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Static shared memory access with one piece of input data to be reused for successive execution of one instruction in a reconfigurable parallel processor [patent_app_type] => utility [patent_app_number] => 15/919774 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 35 [patent_no_of_words] => 19817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919774 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/919774
Static shared memory access with one piece of input data to be reused for successive execution of one instruction in a reconfigurable parallel processor Mar 12, 2018 Issued
Array ( [id] => 16307518 [patent_doc_number] => 10776312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Shared memory access for a reconfigurable parallel processor with a plurality of chained memory ports [patent_app_type] => utility [patent_app_number] => 15/919752 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 35 [patent_no_of_words] => 19541 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919752 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/919752
Shared memory access for a reconfigurable parallel processor with a plurality of chained memory ports Mar 12, 2018 Issued
Array ( [id] => 16217325 [patent_doc_number] => 10733139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Private memory access for a reconfigurable parallel processor using a plurality of chained memory ports [patent_app_type] => utility [patent_app_number] => 15/919727 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 35 [patent_no_of_words] => 19835 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919727 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/919727
Private memory access for a reconfigurable parallel processor using a plurality of chained memory ports Mar 12, 2018 Issued
Array ( [id] => 16307517 [patent_doc_number] => 10776311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Circular reconfiguration for a reconfigurable parallel processor using a plurality of chained memory ports [patent_app_type] => utility [patent_app_number] => 15/919709 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 35 [patent_no_of_words] => 20025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919709 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/919709
Circular reconfiguration for a reconfigurable parallel processor using a plurality of chained memory ports Mar 12, 2018 Issued
Array ( [id] => 13579887 [patent_doc_number] => 20180341492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => PROCESSOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/916035 [patent_app_country] => US [patent_app_date] => 2018-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916035 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/916035
Branch destination prediction based on accord or discord of previous load data from a data cache line corresponding to a load instruction and present load data Mar 7, 2018 Issued
Array ( [id] => 14750623 [patent_doc_number] => 20190258485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => BRANCH PREDICTION [patent_app_type] => utility [patent_app_number] => 15/900914 [patent_app_country] => US [patent_app_date] => 2018-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900914 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/900914
Performing at least two branch predictions for non-contiguous instruction blocks at the same time using a prediction mapping Feb 20, 2018 Issued
Array ( [id] => 13511901 [patent_doc_number] => 20180307493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => ENHANCED MANAGED RUNTIME ENVIRONMENTS THAT SUPPORT DETERMINISTIC RECORD AND REPLAY [patent_app_type] => utility [patent_app_number] => 15/897974 [patent_app_country] => US [patent_app_date] => 2018-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15897974 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/897974
Enhanced managed runtime environments that support deterministic record and replay Feb 14, 2018 Issued
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