Search

Keith E. Vicary

Examiner (ID: 17556)

Most Active Art Unit
2183
Art Unit(s)
2183, 2182
Total Applications
813
Issued Applications
433
Pending Applications
82
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13992247 [patent_doc_number] => 20190065281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => TECHNOLOGIES FOR AUTO-MIGRATION IN ACCELERATED ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 15/859385 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859385 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859385
TECHNOLOGIES FOR AUTO-MIGRATION IN ACCELERATED ARCHITECTURES Dec 29, 2017 Abandoned
Array ( [id] => 14506331 [patent_doc_number] => 20190196820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => APPARATUS AND METHOD FOR RIGHT SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED DOUBLEWORDS [patent_app_type] => utility [patent_app_number] => 15/850765 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850765 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/850765
APPARATUS AND METHOD FOR RIGHT SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED DOUBLEWORDS Dec 20, 2017 Abandoned
Array ( [id] => 14506347 [patent_doc_number] => 20190196828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => APPARATUS AND METHOD FOR VECTOR MULTIPLY OF SIGNED WORDS, ROUNDING, AND SATURATION [patent_app_type] => utility [patent_app_number] => 15/850248 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13915 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850248 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/850248
APPARATUS AND METHOD FOR VECTOR MULTIPLY OF SIGNED WORDS, ROUNDING, AND SATURATION Dec 20, 2017 Abandoned
Array ( [id] => 15248255 [patent_doc_number] => 10509652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => In-lane vector shuffle instructions [patent_app_type] => utility [patent_app_number] => 15/849711 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4963 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849711 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849711
In-lane vector shuffle instructions Dec 20, 2017 Issued
Array ( [id] => 15284509 [patent_doc_number] => 10514918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => In-lane vector shuffle instructions [patent_app_type] => utility [patent_app_number] => 15/849710 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4963 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 486 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849710 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849710
In-lane vector shuffle instructions Dec 20, 2017 Issued
Array ( [id] => 14506335 [patent_doc_number] => 20190196822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => APPARATUS AND METHOD FOR SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED WORDS [patent_app_type] => utility [patent_app_number] => 15/851145 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15851145 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/851145
APPARATUS AND METHOD FOR SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED WORDS Dec 20, 2017 Abandoned
Array ( [id] => 14506349 [patent_doc_number] => 20190196829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => APPARATUS AND METHOD FOR VECTOR MULTIPLY AND SUBTRACTION OF SIGNED DOUBLEWORDS [patent_app_type] => utility [patent_app_number] => 15/850687 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850687 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/850687
APPARATUS AND METHOD FOR VECTOR MULTIPLY AND SUBTRACTION OF SIGNED DOUBLEWORDS Dec 20, 2017 Abandoned
Array ( [id] => 16431395 [patent_doc_number] => 10831477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => In-lane vector shuffle instructions [patent_app_type] => utility [patent_app_number] => 15/849715 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4963 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 424 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849715 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849715
In-lane vector shuffle instructions Dec 20, 2017 Issued
Array ( [id] => 14506265 [patent_doc_number] => 20190196787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => APPARATUS AND METHOD FOR RIGHT SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED DOUBLEWORDS [patent_app_type] => utility [patent_app_number] => 15/850682 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/850682
APPARATUS AND METHOD FOR RIGHT SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED DOUBLEWORDS Dec 20, 2017 Abandoned
Array ( [id] => 14506333 [patent_doc_number] => 20190196821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => APPARATUS AND METHOD FOR RIGHT-SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED WORDS [patent_app_type] => utility [patent_app_number] => 15/850949 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850949 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/850949
APPARATUS AND METHOD FOR RIGHT-SHIFTING PACKED QUADWORDS AND EXTRACTING PACKED WORDS Dec 20, 2017 Abandoned
Array ( [id] => 16972302 [patent_doc_number] => 11068274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Prioritized instructions in an instruction completion table of a simultaneous multithreading processor [patent_app_type] => utility [patent_app_number] => 15/843982 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15843982 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/843982
Prioritized instructions in an instruction completion table of a simultaneous multithreading processor Dec 14, 2017 Issued
Array ( [id] => 14379127 [patent_doc_number] => 20190163476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES HANDLING HALF-PRECISION OPERANDS [patent_app_type] => utility [patent_app_number] => 15/824902 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8940 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824902 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824902
SYSTEMS, METHODS, AND APPARATUSES HANDLING HALF-PRECISION OPERANDS Nov 27, 2017 Abandoned
Array ( [id] => 14379159 [patent_doc_number] => 20190163492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => EMPLOYING A STACK ACCELERATOR FOR STACK-TYPE ACCESSES [patent_app_type] => utility [patent_app_number] => 15/824649 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824649 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824649
EMPLOYING A STACK ACCELERATOR FOR STACK-TYPE ACCESSES Nov 27, 2017 Abandoned
Array ( [id] => 16462747 [patent_doc_number] => 10846095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => System and method for processing a load micro-operation by allocating an address generation scheduler queue entry without allocating a load queue entry [patent_app_type] => utility [patent_app_number] => 15/824729 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3235 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824729 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824729
System and method for processing a load micro-operation by allocating an address generation scheduler queue entry without allocating a load queue entry Nov 27, 2017 Issued
Array ( [id] => 16551589 [patent_doc_number] => 10884748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Providing a predicted target address to multiple locations based on detecting an affiliated relationship [patent_app_type] => utility [patent_app_number] => 15/816363 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 34 [patent_no_of_words] => 19168 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15816363 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/816363
Providing a predicted target address to multiple locations based on detecting an affiliated relationship Nov 16, 2017 Issued
Array ( [id] => 13497183 [patent_doc_number] => 20180300134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => SYSTEM AND METHOD OF EXECUTING CACHE LINE UNALIGNED LOAD INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 15/810798 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810798 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/810798
SYSTEM AND METHOD OF EXECUTING CACHE LINE UNALIGNED LOAD INSTRUCTIONS Nov 12, 2017 Abandoned
Array ( [id] => 15284507 [patent_doc_number] => 10514917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => In-lane vector shuffle instructions [patent_app_type] => utility [patent_app_number] => 15/801652 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4958 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 452 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15801652 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/801652
In-lane vector shuffle instructions Nov 1, 2017 Issued
Array ( [id] => 13906069 [patent_doc_number] => 20190042239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => MANAGING AN ISSUE QUEUE FOR FUSED INSTRUCTIONS AND PAIRED INSTRUCTIONS IN A MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 15/795772 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15795772 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/795772
Managing an issue queue for fused instructions and paired instructions in a microprocessor Oct 26, 2017 Issued
Array ( [id] => 14135607 [patent_doc_number] => 20190102193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => APPARATUS AND METHOD FOR COMPLEX BY COMPLEX CONJUGATE MULTIPLICATION [patent_app_type] => utility [patent_app_number] => 15/721448 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721448 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721448
Apparatus and method for complex by complex conjugate multiplication Sep 28, 2017 Issued
Array ( [id] => 16037075 [patent_doc_number] => 10680977 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-09 [patent_title] => Splitting data into an information vector and a control vector and processing, at a stage of a control pipeline, the control vector and a data block of the information vector extracted from a corresponding stage of a data pipeline [patent_app_type] => utility [patent_app_number] => 15/716367 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13637 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716367 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716367
Splitting data into an information vector and a control vector and processing, at a stage of a control pipeline, the control vector and a data block of the information vector extracted from a corresponding stage of a data pipeline Sep 25, 2017 Issued
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