Search

Keith E. Vicary

Examiner (ID: 17556)

Most Active Art Unit
2183
Art Unit(s)
2183, 2182
Total Applications
813
Issued Applications
433
Pending Applications
82
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12311283 [patent_doc_number] => 09940139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Split-level history buffer in a computer processing unit [patent_app_type] => utility [patent_app_number] => 15/270275 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7594 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270275 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270275
Split-level history buffer in a computer processing unit Sep 19, 2016 Issued
Array ( [id] => 16045975 [patent_doc_number] => 10684859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Providing memory dependence prediction in block-atomic dataflow architectures [patent_app_type] => utility [patent_app_number] => 15/269254 [patent_app_country] => US [patent_app_date] => 2016-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8797 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15269254 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/269254
Providing memory dependence prediction in block-atomic dataflow architectures Sep 18, 2016 Issued
Array ( [id] => 13679527 [patent_doc_number] => 20160378500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => SPLIT-LEVEL HISTORY BUFFER IN A COMPUTER PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 15/267650 [patent_app_country] => US [patent_app_date] => 2016-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267650 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/267650
Split-level history buffer in a computer processing unit Sep 15, 2016 Issued
Array ( [id] => 12241965 [patent_doc_number] => 20180074827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'Instruction and Logic for Dynamic Store Elimination' [patent_app_type] => utility [patent_app_number] => 15/265587 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 34214 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15265587 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/265587
Eliminating redundant stores using a protection designator and a clear designator Sep 13, 2016 Issued
Array ( [id] => 12241961 [patent_doc_number] => 20180074824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'Outer Product Engine' [patent_app_type] => utility [patent_app_number] => 15/264002 [patent_app_country] => US [patent_app_date] => 2016-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15264002 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/264002
Outer Product Engine Sep 12, 2016 Abandoned
Array ( [id] => 12234886 [patent_doc_number] => 20180067749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'TRACING PROCESSING ACTIVITY' [patent_app_type] => utility [patent_app_number] => 15/258058 [patent_app_country] => US [patent_app_date] => 2016-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8644 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15258058 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/258058
Tracing processing activity with position data to reorder items of trace data Sep 6, 2016 Issued
Array ( [id] => 17046669 [patent_doc_number] => 11099849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Method for reducing fetch cycles for return-type instructions [patent_app_type] => utility [patent_app_number] => 15/254648 [patent_app_country] => US [patent_app_date] => 2016-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9108 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15254648 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/254648
Method for reducing fetch cycles for return-type instructions Aug 31, 2016 Issued
Array ( [id] => 11292485 [patent_doc_number] => 20160342417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'PROVIDING VECTOR SUB-BYTE DECOMPRESSION FUNCTIONALITY' [patent_app_type] => utility [patent_app_number] => 15/225401 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 27424 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225401 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225401
PROVIDING VECTOR SUB-BYTE DECOMPRESSION FUNCTIONALITY Jul 31, 2016 Abandoned
Array ( [id] => 12053371 [patent_doc_number] => 20170329715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'HAZARD AVOIDANCE IN A MULTI-SLICE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/220028 [patent_app_country] => US [patent_app_date] => 2016-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7893 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15220028 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/220028
HAZARD AVOIDANCE IN A MULTI-SLICE PROCESSOR Jul 25, 2016 Abandoned
Array ( [id] => 11077950 [patent_doc_number] => 20160274914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'PROCESSORS WITH BRANCH INSTRUCTION, CIRCUITS, SYSTEMS AND PROCESSES OF MANUFACTURE AND OPERATION' [patent_app_type] => utility [patent_app_number] => 15/169277 [patent_app_country] => US [patent_app_date] => 2016-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 19879 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169277 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/169277
Circuit, system, and method for determining whether a branch instruction is predicted based on a capture range of a second instruction May 30, 2016 Issued
Array ( [id] => 12986011 [patent_doc_number] => 20170344364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => SYSTEM AND METHOD FOR DATA COMPATIBILITY ACROSS HETEROGENEOUS MACHINE ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 15/164724 [patent_app_country] => US [patent_app_date] => 2016-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15164724 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/164724
SYSTEM AND METHOD FOR DATA COMPATIBILITY ACROSS HETEROGENEOUS MACHINE ARCHITECTURES May 24, 2016 Abandoned
Array ( [id] => 12986371 [patent_doc_number] => 20170344485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => HETEROGENEOUS RUNAHEAD CORE FOR DATA ANALYTICS [patent_app_type] => utility [patent_app_number] => 15/164551 [patent_app_country] => US [patent_app_date] => 2016-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15164551 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/164551
HETEROGENEOUS RUNAHEAD CORE FOR DATA ANALYTICS May 24, 2016 Abandoned
Array ( [id] => 12053263 [patent_doc_number] => 20170329607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'HAZARD AVOIDANCE IN A MULTI-SLICE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/155327 [patent_app_country] => US [patent_app_date] => 2016-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7863 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15155327 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/155327
HAZARD AVOIDANCE IN A MULTI-SLICE PROCESSOR May 15, 2016 Abandoned
Array ( [id] => 11352346 [patent_doc_number] => 20160371087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'SPLIT-LEVEL HISTORY BUFFER IN A COMPUTER PROCESSING UNIT' [patent_app_type] => utility [patent_app_number] => 15/091788 [patent_app_country] => US [patent_app_date] => 2016-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7708 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15091788 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/091788
Split-level history buffer in a computer processing unit Apr 5, 2016 Issued
Array ( [id] => 15671561 [patent_doc_number] => 10600014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Facilitating provisioning in a mixed environment of locales [patent_app_type] => utility [patent_app_number] => 15/011319 [patent_app_country] => US [patent_app_date] => 2016-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3342 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15011319 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/011319
Facilitating provisioning in a mixed environment of locales Jan 28, 2016 Issued
Array ( [id] => 11708840 [patent_doc_number] => 20170177338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'MANAGEMENT OF ASYNCHRONOUS INTERRUPTS IN A TRANSACTIONAL MEMORY MULTIPROCESSOR ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 14/974381 [patent_app_country] => US [patent_app_date] => 2015-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 16998 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14974381 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/974381
MANAGEMENT OF ASYNCHRONOUS INTERRUPTS IN A TRANSACTIONAL MEMORY MULTIPROCESSOR ENVIRONMENT Dec 17, 2015 Abandoned
Array ( [id] => 11516270 [patent_doc_number] => 20170083343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'OUT OF ORDER COMMIT' [patent_app_type] => utility [patent_app_number] => 14/942461 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 22126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942461 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/942461
OUT OF ORDER COMMIT Nov 15, 2015 Abandoned
Array ( [id] => 11606490 [patent_doc_number] => 20170123793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'ENABLING REMOVAL AND RECONSTRUCTION OF FLAG OPERATIONS IN A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/930848 [patent_app_country] => US [patent_app_date] => 2015-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 21780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14930848 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/930848
Enabling removal and reconstruction of flag operations in a processor Nov 2, 2015 Issued
Array ( [id] => 18445961 [patent_doc_number] => 11681531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Generation and use of memory access instruction order encodings [patent_app_type] => utility [patent_app_number] => 14/921855 [patent_app_country] => US [patent_app_date] => 2015-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 17513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14921855 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/921855
Generation and use of memory access instruction order encodings Oct 22, 2015 Issued
Array ( [id] => 16171569 [patent_doc_number] => 10713139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => System level testing of multi-threading functionality including building independent instruction streams while honoring architecturally imposed common fields and constraints [patent_app_type] => utility [patent_app_number] => 14/869641 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8460 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 448 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14869641 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/869641
System level testing of multi-threading functionality including building independent instruction streams while honoring architecturally imposed common fields and constraints Sep 28, 2015 Issued
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