Search

Keith E. Vicary

Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
798
Issued Applications
429
Pending Applications
76
Abandoned Applications
310

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16355173 [patent_doc_number] => 10795683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Predicting indirect branches using problem branch filtering and pattern cache [patent_app_type] => utility [patent_app_number] => 14/301936 [patent_app_country] => US [patent_app_date] => 2014-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5772 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 439 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14301936 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/301936
Predicting indirect branches using problem branch filtering and pattern cache Jun 10, 2014 Issued
Array ( [id] => 9742994 [patent_doc_number] => 20140278714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'SYSTEM, APPARATUS, AND METHOD FOR FACILITATING PROVISIONING IN A MIXED ENVIRONMENT OF LOCALES' [patent_app_type] => utility [patent_app_number] => 14/288020 [patent_app_country] => US [patent_app_date] => 2014-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3474 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14288020 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/288020
Facilitating provisioning in a mixed environment of locales May 26, 2014 Issued
Array ( [id] => 17180184 [patent_doc_number] => 11157428 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-26 [patent_title] => Architecture and programming in a parallel processing environment with a tiled processor having a direct memory access controller [patent_app_type] => utility [patent_app_number] => 14/180749 [patent_app_country] => US [patent_app_date] => 2014-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 15306 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14180749 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/180749
Architecture and programming in a parallel processing environment with a tiled processor having a direct memory access controller Feb 13, 2014 Issued
Array ( [id] => 13212925 [patent_doc_number] => 10120833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Processor and method for dynamically allocating processing elements to front end units using a plurality of registers [patent_app_type] => utility [patent_app_number] => 14/165881 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 13158 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14165881 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/165881
Processor and method for dynamically allocating processing elements to front end units using a plurality of registers Jan 27, 2014 Issued
Array ( [id] => 9465375 [patent_doc_number] => 20140129802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'METHODS, APPARATUS, AND INSTRUCTIONS FOR PROCESSING VECTOR DATA' [patent_app_type] => utility [patent_app_number] => 14/152698 [patent_app_country] => US [patent_app_date] => 2014-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5149 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14152698 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/152698
METHODS, APPARATUS, AND INSTRUCTIONS FOR PROCESSING VECTOR DATA Jan 9, 2014 Abandoned
Array ( [id] => 10258079 [patent_doc_number] => 20150143076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'VECTOR PROCESSING ENGINES (VPEs) EMPLOYING DESPREADING CIRCUITRY IN DATA FLOW PATHS BETWEEN EXECUTION UNITS AND VECTOR DATA MEMORY TO PROVIDE IN-FLIGHT DESPREADING OF SPREAD-SPECTRUM SEQUENCES, AND RELATED VECTOR PROCESSING INSTRUCTIONS, SYSTEMS, AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/082067 [patent_app_country] => US [patent_app_date] => 2013-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 55342 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082067 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/082067
VECTOR PROCESSING ENGINES (VPEs) EMPLOYING DESPREADING CIRCUITRY IN DATA FLOW PATHS BETWEEN EXECUTION UNITS AND VECTOR DATA MEMORY TO PROVIDE IN-FLIGHT DESPREADING OF SPREAD-SPECTRUM SEQUENCES, AND RELATED VECTOR PROCESSING INSTRUCTIONS, SYSTEMS, AND METHODS Nov 14, 2013 Abandoned
Array ( [id] => 9688207 [patent_doc_number] => 20140244972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'METHOD AND APPARATUS FOR GAME PHYSICS CONCURRENT COMPUTATIONS' [patent_app_type] => utility [patent_app_number] => 14/070968 [patent_app_country] => US [patent_app_date] => 2013-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5010 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14070968 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/070968
METHOD AND APPARATUS FOR GAME PHYSICS CONCURRENT COMPUTATIONS Nov 3, 2013 Abandoned
Array ( [id] => 14364353 [patent_doc_number] => 10303480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Unified store queue for reducing linear aliasing effects [patent_app_type] => utility [patent_app_number] => 14/067564 [patent_app_country] => US [patent_app_date] => 2013-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9108 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14067564 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/067564
Unified store queue for reducing linear aliasing effects Oct 29, 2013 Issued
Array ( [id] => 13891435 [patent_doc_number] => 10198265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Microprocessor for gating a load operation based on entries of a prediction table [patent_app_type] => utility [patent_app_number] => 14/063173 [patent_app_country] => US [patent_app_date] => 2013-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 13044 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14063173 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/063173
Microprocessor for gating a load operation based on entries of a prediction table Oct 24, 2013 Issued
Array ( [id] => 13281485 [patent_doc_number] => 10152327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Apparatus for gating a load operation based on entries of a prediction table [patent_app_type] => utility [patent_app_number] => 14/063409 [patent_app_country] => US [patent_app_date] => 2013-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 13081 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14063409 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/063409
Apparatus for gating a load operation based on entries of a prediction table Oct 24, 2013 Issued
Array ( [id] => 10236044 [patent_doc_number] => 20150121038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'PREFETCH STRATEGY CONTROL' [patent_app_type] => utility [patent_app_number] => 14/061837 [patent_app_country] => US [patent_app_date] => 2013-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3161 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061837 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/061837
Prefetch strategy control for parallel execution of threads based on one or more characteristics of a stream of program instructions indicative that a data access instruction within a program is scheduled to be executed a plurality of times Oct 23, 2013 Issued
Array ( [id] => 10228261 [patent_doc_number] => 20150113254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'EFFICIENCY THROUGH A DISTRIBUTED INSTRUCTION SET ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/061666 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6830 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061666 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/061666
Dispatching a stored instruction in response to determining that a received instruction is of a same instruction type Oct 22, 2013 Issued
Array ( [id] => 9520481 [patent_doc_number] => 20140156973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'PROCESSOR AND CONTROL METHOD OF PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/060050 [patent_app_country] => US [patent_app_date] => 2013-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16397 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14060050 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/060050
PROCESSOR AND CONTROL METHOD OF PROCESSOR Oct 21, 2013 Abandoned
Array ( [id] => 9774333 [patent_doc_number] => 20140297995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'FAULT-TOLERANT SYSTEM AND FAULT-TOLERANT OPERATING METHOD' [patent_app_type] => utility [patent_app_number] => 14/054643 [patent_app_country] => US [patent_app_date] => 2013-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8267 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14054643 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/054643
Fault-tolerant system and fault-tolerant operating method capable of synthesizing result by at least two calculation modules Oct 14, 2013 Issued
Array ( [id] => 10215772 [patent_doc_number] => 20150100764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'DYNAMICALLY DETECTING UNIFORMITY AND ELIMINATING REDUNDANT COMPUTATIONS TO REDUCE POWER CONSUMPTION' [patent_app_type] => utility [patent_app_number] => 14/048647 [patent_app_country] => US [patent_app_date] => 2013-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14048647 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/048647
Dynamically detecting uniformity and eliminating redundant computations to reduce power consumption Oct 7, 2013 Issued
Array ( [id] => 9282913 [patent_doc_number] => 20140032881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'INSTRUCTION AND LOGIC FOR PERFORMING A DOT-PRODUCT OPERATION' [patent_app_type] => utility [patent_app_number] => 14/042696 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12128 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14042696 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/042696
INSTRUCTION AND LOGIC FOR PERFORMING A DOT-PRODUCT OPERATION Sep 29, 2013 Abandoned
Array ( [id] => 9282656 [patent_doc_number] => 20140032624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'INSTRUCTION AND LOGIC FOR PERFORMING A DOT-PRODUCT OPERATION' [patent_app_type] => utility [patent_app_number] => 14/042681 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12229 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14042681 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/042681
INSTRUCTION AND LOGIC FOR PERFORMING A DOT-PRODUCT OPERATION Sep 29, 2013 Abandoned
Array ( [id] => 10204201 [patent_doc_number] => 20150089189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'Predicate Vector Pack and Unpack Instructions' [patent_app_type] => utility [patent_app_number] => 14/034629 [patent_app_country] => US [patent_app_date] => 2013-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14034629 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/034629
Predicate Vector Pack and Unpack Instructions Sep 23, 2013 Abandoned
Array ( [id] => 9493118 [patent_doc_number] => 20140143524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING APPARATUS CONTROL METHOD, AND A COMPUTER-READABLE STORAGE MEDIUM STORING A CONTROL PROGRAM FOR CONTROLLING AN INFORMATION PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/033983 [patent_app_country] => US [patent_app_date] => 2013-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13646 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14033983 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/033983
INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING APPARATUS CONTROL METHOD, AND A COMPUTER-READABLE STORAGE MEDIUM STORING A CONTROL PROGRAM FOR CONTROLLING AN INFORMATION PROCESSING APPARATUS Sep 22, 2013 Abandoned
Array ( [id] => 14091787 [patent_doc_number] => 10241798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Technique for reducing voltage droop by throttling instruction issue rate [patent_app_type] => utility [patent_app_number] => 14/033378 [patent_app_country] => US [patent_app_date] => 2013-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7157 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14033378 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/033378
Technique for reducing voltage droop by throttling instruction issue rate Sep 19, 2013 Issued
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