Search

Keith E. Vicary

Examiner (ID: 17556)

Most Active Art Unit
2183
Art Unit(s)
2183, 2182
Total Applications
813
Issued Applications
433
Pending Applications
82
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13055153 [patent_doc_number] => 10048967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Processor arranged to operate as a single-threaded (nX)-bit processor and as an n-threaded X-bit processor in different modes of operation [patent_app_type] => utility [patent_app_number] => 14/798841 [patent_app_country] => US [patent_app_date] => 2015-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6829 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14798841 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/798841
Processor arranged to operate as a single-threaded (nX)-bit processor and as an n-threaded X-bit processor in different modes of operation Jul 13, 2015 Issued
Array ( [id] => 13679523 [patent_doc_number] => 20160378498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => Systems, Methods, and Apparatuses for Last Branch Record Support [patent_app_type] => utility [patent_app_number] => 14/752891 [patent_app_country] => US [patent_app_date] => 2015-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752891 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752891
Systems, methods, and apparatuses for last branch record support compatible with binary translation and speculative execution using an architectural bit array and a write bit array Jun 26, 2015 Issued
Array ( [id] => 14091791 [patent_doc_number] => 10241800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Split-level history buffer in a computer processing unit [patent_app_type] => utility [patent_app_number] => 14/740694 [patent_app_country] => US [patent_app_date] => 2015-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7339 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14740694 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/740694
Split-level history buffer in a computer processing unit Jun 15, 2015 Issued
Array ( [id] => 10376535 [patent_doc_number] => 20150261541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'DYNAMIC REGISTER MACHINE' [patent_app_type] => utility [patent_app_number] => 14/696467 [patent_app_country] => US [patent_app_date] => 2015-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 47241 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14696467 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/696467
DYNAMIC REGISTER MACHINE Apr 25, 2015 Abandoned
Array ( [id] => 15670419 [patent_doc_number] => 10599439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Method and device for allocating a VLIW instruction based on slot information stored in a database by a calculation allocation instruction [patent_app_type] => utility [patent_app_number] => 15/125023 [patent_app_country] => US [patent_app_date] => 2015-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6144 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15125023 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/125023
Method and device for allocating a VLIW instruction based on slot information stored in a database by a calculation allocation instruction Mar 10, 2015 Issued
Array ( [id] => 11062682 [patent_doc_number] => 20160259644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'OPTIMIZED MODE TRANSITIONS THROUGH PREDICTING TARGET STATE' [patent_app_type] => utility [patent_app_number] => 14/639004 [patent_app_country] => US [patent_app_date] => 2015-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13054 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14639004 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/639004
Optimized mode transitions through predicting target state Mar 3, 2015 Issued
Array ( [id] => 11035048 [patent_doc_number] => 20160232005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'SYSTEM LEVEL TESTING OF MULTI-THREADING FUNCTIONALITY' [patent_app_type] => utility [patent_app_number] => 14/618693 [patent_app_country] => US [patent_app_date] => 2015-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8692 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14618693 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/618693
System level testing of multi-threading functionality including building independent instruction streams while honoring architecturally imposed common fields and constraints Feb 9, 2015 Issued
Array ( [id] => 10342361 [patent_doc_number] => 20150227366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'PROCESSOR WITH GRANULAR ADD IMMEDIATES CAPABILITY & METHODS' [patent_app_type] => utility [patent_app_number] => 14/612077 [patent_app_country] => US [patent_app_date] => 2015-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10996 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612077 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/612077
PROCESSOR WITH GRANULAR ADD IMMEDIATES CAPABILITY & METHODS Feb 1, 2015 Abandoned
Array ( [id] => 10258084 [patent_doc_number] => 20150143081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'PROCESSOR CAPABLE OF SUPPORTING MULTIMODE AND MULTIMODE SUPPORTING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/606240 [patent_app_country] => US [patent_app_date] => 2015-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 13341 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14606240 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/606240
PROCESSOR CAPABLE OF SUPPORTING MULTIMODE AND MULTIMODE SUPPORTING METHOD THEREOF Jan 26, 2015
Array ( [id] => 10680463 [patent_doc_number] => 20160026607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'PARALLELIZATION OF SCALAR OPERATIONS BY VECTOR PROCESSORS USING DATA-INDEXED ACCUMULATORS IN VECTOR REGISTER FILES, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA' [patent_app_type] => utility [patent_app_number] => 14/486326 [patent_app_country] => US [patent_app_date] => 2014-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7672 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14486326 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/486326
PARALLELIZATION OF SCALAR OPERATIONS BY VECTOR PROCESSORS USING DATA-INDEXED ACCUMULATORS IN VECTOR REGISTER FILES, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA Sep 14, 2014 Abandoned
Array ( [id] => 10708857 [patent_doc_number] => 20160055004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'METHOD AND APPARATUS FOR NON-SPECULATIVE FETCH AND EXECUTION OF CONTROL-DEPENDENT BLOCKS' [patent_app_type] => utility [patent_app_number] => 14/465652 [patent_app_country] => US [patent_app_date] => 2014-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12833 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14465652 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/465652
METHOD AND APPARATUS FOR NON-SPECULATIVE FETCH AND EXECUTION OF CONTROL-DEPENDENT BLOCKS Aug 20, 2014 Abandoned
Array ( [id] => 14175847 [patent_doc_number] => 10261939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Performing lookup table operations on a single-instruction multiple data processor [patent_app_type] => utility [patent_app_number] => 14/464134 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464134 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/464134
Performing lookup table operations on a single-instruction multiple data processor Aug 19, 2014 Issued
Array ( [id] => 10708854 [patent_doc_number] => 20160055001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'LOW POWER INSTRUCTION BUFFER FOR HIGH PERFORMANCE PROCESSORS' [patent_app_type] => utility [patent_app_number] => 14/463270 [patent_app_country] => US [patent_app_date] => 2014-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14463270 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/463270
LOW POWER INSTRUCTION BUFFER FOR HIGH PERFORMANCE PROCESSORS Aug 18, 2014 Abandoned
Array ( [id] => 10383954 [patent_doc_number] => 20150268961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'DECOUPLING L2 BTB FROM L2 CACHE TO ACCELERATE SEARCH FOR MISS AFTER MISS' [patent_app_type] => utility [patent_app_number] => 14/463638 [patent_app_country] => US [patent_app_date] => 2014-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14463638 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/463638
DECOUPLING L2 BTB FROM L2 CACHE TO ACCELERATE SEARCH FOR MISS AFTER MISS Aug 18, 2014 Abandoned
Array ( [id] => 10485545 [patent_doc_number] => 20150370564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'APPARATUS AND METHOD FOR ADDING A PROGRAMMABLE SHORT DELAY' [patent_app_type] => utility [patent_app_number] => 14/313810 [patent_app_country] => US [patent_app_date] => 2014-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6508 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14313810 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/313810
APPARATUS AND METHOD FOR ADDING A PROGRAMMABLE SHORT DELAY Jun 23, 2014 Abandoned
Array ( [id] => 16355173 [patent_doc_number] => 10795683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Predicting indirect branches using problem branch filtering and pattern cache [patent_app_type] => utility [patent_app_number] => 14/301936 [patent_app_country] => US [patent_app_date] => 2014-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5772 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 439 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14301936 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/301936
Predicting indirect branches using problem branch filtering and pattern cache Jun 10, 2014 Issued
Array ( [id] => 9742994 [patent_doc_number] => 20140278714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'SYSTEM, APPARATUS, AND METHOD FOR FACILITATING PROVISIONING IN A MIXED ENVIRONMENT OF LOCALES' [patent_app_type] => utility [patent_app_number] => 14/288020 [patent_app_country] => US [patent_app_date] => 2014-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3474 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14288020 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/288020
Facilitating provisioning in a mixed environment of locales May 26, 2014 Issued
Array ( [id] => 17180184 [patent_doc_number] => 11157428 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-26 [patent_title] => Architecture and programming in a parallel processing environment with a tiled processor having a direct memory access controller [patent_app_type] => utility [patent_app_number] => 14/180749 [patent_app_country] => US [patent_app_date] => 2014-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 15306 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14180749 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/180749
Architecture and programming in a parallel processing environment with a tiled processor having a direct memory access controller Feb 13, 2014 Issued
Array ( [id] => 13212925 [patent_doc_number] => 10120833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Processor and method for dynamically allocating processing elements to front end units using a plurality of registers [patent_app_type] => utility [patent_app_number] => 14/165881 [patent_app_country] => US [patent_app_date] => 2014-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 13158 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14165881 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/165881
Processor and method for dynamically allocating processing elements to front end units using a plurality of registers Jan 27, 2014 Issued
Array ( [id] => 9465375 [patent_doc_number] => 20140129802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'METHODS, APPARATUS, AND INSTRUCTIONS FOR PROCESSING VECTOR DATA' [patent_app_type] => utility [patent_app_number] => 14/152698 [patent_app_country] => US [patent_app_date] => 2014-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5149 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14152698 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/152698
METHODS, APPARATUS, AND INSTRUCTIONS FOR PROCESSING VECTOR DATA Jan 9, 2014 Abandoned
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