Keith E. Vicary

Array ( [id] => 10258079 [patent_doc_number] => 20150143076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'VECTOR PROCESSING ENGINES (VPEs) EMPLOYING DESPREADING CIRCUITRY IN DATA FLOW PATHS BETWEEN EXECUTION UNITS AND VECTOR DATA MEMORY TO PROVIDE IN-FLIGHT DESPREADING OF SPREAD-SPECTRUM SEQUENCES, AND RELATED VECTOR PROCESSING INSTRUCTIONS, SYSTEMS, AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/082067 [patent_app_country] => US [patent_app_date] => 2013-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 55342 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9688207 [patent_doc_number] => 20140244972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'METHOD AND APPARATUS FOR GAME PHYSICS CONCURRENT COMPUTATIONS' [patent_app_type] => utility [patent_app_number] => 14/070968 [patent_app_country] => US [patent_app_date] => 2013-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5010 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14070968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14364353 [patent_doc_number] => 10303480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Unified store queue for reducing linear aliasing effects [patent_app_type] => utility [patent_app_number] => 14/067564 [patent_app_country] => US [patent_app_date] => 2013-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9108 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14067564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13281485 [patent_doc_number] => 10152327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Apparatus for gating a load operation based on entries of a prediction table [patent_app_type] => utility [patent_app_number] => 14/063409 [patent_app_country] => US [patent_app_date] => 2013-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 13081 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14063409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13891435 [patent_doc_number] => 10198265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Microprocessor for gating a load operation based on entries of a prediction table [patent_app_type] => utility [patent_app_number] => 14/063173 [patent_app_country] => US [patent_app_date] => 2013-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 13044 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14063173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10236044 [patent_doc_number] => 20150121038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'PREFETCH STRATEGY CONTROL' [patent_app_type] => utility [patent_app_number] => 14/061837 [patent_app_country] => US [patent_app_date] => 2013-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3161 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10228261 [patent_doc_number] => 20150113254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'EFFICIENCY THROUGH A DISTRIBUTED INSTRUCTION SET ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/061666 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6830 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9520481 [patent_doc_number] => 20140156973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'PROCESSOR AND CONTROL METHOD OF PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/060050 [patent_app_country] => US [patent_app_date] => 2013-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16397 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14060050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9774333 [patent_doc_number] => 20140297995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'FAULT-TOLERANT SYSTEM AND FAULT-TOLERANT OPERATING METHOD' [patent_app_type] => utility [patent_app_number] => 14/054643 [patent_app_country] => US [patent_app_date] => 2013-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8267 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14054643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10215772 [patent_doc_number] => 20150100764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'DYNAMICALLY DETECTING UNIFORMITY AND ELIMINATING REDUNDANT COMPUTATIONS TO REDUCE POWER CONSUMPTION' [patent_app_type] => utility [patent_app_number] => 14/048647 [patent_app_country] => US [patent_app_date] => 2013-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14048647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9282913 [patent_doc_number] => 20140032881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'INSTRUCTION AND LOGIC FOR PERFORMING A DOT-PRODUCT OPERATION' [patent_app_type] => utility [patent_app_number] => 14/042696 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12128 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14042696 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9282656 [patent_doc_number] => 20140032624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'INSTRUCTION AND LOGIC FOR PERFORMING A DOT-PRODUCT OPERATION' [patent_app_type] => utility [patent_app_number] => 14/042681 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12229 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14042681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10204201 [patent_doc_number] => 20150089189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'Predicate Vector Pack and Unpack Instructions' [patent_app_type] => utility [patent_app_number] => 14/034629 [patent_app_country] => US [patent_app_date] => 2013-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14034629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9493118 [patent_doc_number] => 20140143524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING APPARATUS CONTROL METHOD, AND A COMPUTER-READABLE STORAGE MEDIUM STORING A CONTROL PROGRAM FOR CONTROLLING AN INFORMATION PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/033983 [patent_app_country] => US [patent_app_date] => 2013-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13646 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14033983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14091787 [patent_doc_number] => 10241798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Technique for reducing voltage droop by throttling instruction issue rate [patent_app_type] => utility [patent_app_number] => 14/033378 [patent_app_country] => US [patent_app_date] => 2013-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7157 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14033378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9225216 [patent_doc_number] => 20140019991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'ENHANCED MICROPROCESSOR OR MICROCONTROLLER' [patent_app_type] => utility [patent_app_number] => 14/028458 [patent_app_country] => US [patent_app_date] => 2013-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8313 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14028458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9903402 [patent_doc_number] => 20150058602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'PROCESSOR WITH ADAPTIVE PIPELINE LENGTH' [patent_app_type] => utility [patent_app_number] => 13/974571 [patent_app_country] => US [patent_app_date] => 2013-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2989 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13974571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11917258 [patent_doc_number] => 09785444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Hardware accelerator configuration by a translation of configuration data' [patent_app_type] => utility [patent_app_number] => 13/968844 [patent_app_country] => US [patent_app_date] => 2013-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13968844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9897131 [patent_doc_number] => 20150052330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'VECTOR ARITHMETIC REDUCTION' [patent_app_type] => utility [patent_app_number] => 13/967191 [patent_app_country] => US [patent_app_date] => 2013-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 21769 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13967191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11659039 [patent_doc_number] => 09672041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Method for compressing variable-length instructions including PC-relative instructions and processor for executing compressed instructions using an instruction table' [patent_app_type] => utility [patent_app_number] => 13/956382 [patent_app_country] => US [patent_app_date] => 2013-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3258 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13956382 [rel_patent_id] =>[rel_patent_doc_number] =>)