Search

Keith E. Vicary

Examiner (ID: 15210)

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
804
Issued Applications
430
Pending Applications
77
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19617367 [patent_doc_number] => 20240403047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => VECTOR COMPUTATION APPARATUS, PROCESSOR, SYSTEM ON CHIP AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/671202 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671202 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671202
VECTOR COMPUTATION APPARATUS, PROCESSOR, SYSTEM ON CHIP AND ELECTRONIC DEVICE May 21, 2024 Abandoned
Array ( [id] => 19419928 [patent_doc_number] => 20240296051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => APPARATUSES AND METHODS FOR SPECULATIVE EXECUTION SIDE CHANNEL MITIGATION [patent_app_type] => utility [patent_app_number] => 18/661103 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661103 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661103
APPARATUSES AND METHODS FOR SPECULATIVE EXECUTION SIDE CHANNEL MITIGATION May 9, 2024 Pending
Array ( [id] => 20351463 [patent_doc_number] => 20250348315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => Multi-Instruction Packing In Single Instruction Slot [patent_app_type] => utility [patent_app_number] => 18/660925 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660925 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660925
Multi-Instruction Packing In Single Instruction Slot May 9, 2024 Pending
Array ( [id] => 19391385 [patent_doc_number] => 20240281255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => SUPER-THREAD PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/649817 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18649817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/649817
SUPER-THREAD PROCESSOR Apr 28, 2024 Pending
Array ( [id] => 19391381 [patent_doc_number] => 20240281251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => INSTRUCTION LENGTH BASED PARALLEL INSTRUCTION DEMARCATOR [patent_app_type] => utility [patent_app_number] => 18/648259 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648259 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648259
INSTRUCTION LENGTH BASED PARALLEL INSTRUCTION DEMARCATOR Apr 25, 2024 Pending
Array ( [id] => 19334292 [patent_doc_number] => 20240248722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HISTORY RESET OF A PROCESSOR CORE [patent_app_type] => utility [patent_app_number] => 18/626629 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626629 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626629
Apparatuses, methods, and systems for instructions to request a history reset of a processor core Apr 3, 2024 Issued
Array ( [id] => 19481956 [patent_doc_number] => 20240329998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => WAVE LEVEL MATRIX MULTIPLY INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/619392 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619392 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/619392
WAVE LEVEL MATRIX MULTIPLY INSTRUCTIONS Mar 27, 2024 Pending
Array ( [id] => 20281682 [patent_doc_number] => 20250306924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => Apparatus and Method for Remote Atomic Floating Point Operations [patent_app_type] => utility [patent_app_number] => 18/621071 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621071 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/621071
Apparatus and Method for Remote Atomic Floating Point Operations Mar 27, 2024 Pending
Array ( [id] => 19963801 [patent_doc_number] => 12333310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Base plus offset addressing for load/store messages [patent_app_type] => utility [patent_app_number] => 18/620217 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 57 [patent_no_of_words] => 44293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620217 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/620217
Base plus offset addressing for load/store messages Mar 27, 2024 Issued
Array ( [id] => 20145583 [patent_doc_number] => 12379925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Exposing valid byte lanes as vector predicates to CPU [patent_app_type] => utility [patent_app_number] => 18/614947 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 36 [patent_no_of_words] => 21689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614947 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614947
Exposing valid byte lanes as vector predicates to CPU Mar 24, 2024 Issued
Array ( [id] => 20208553 [patent_doc_number] => 20250278273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => ASYNCHRONOUS RELEASE OPERATIONS IN A MULTIPROCESSOR SYSTEM [patent_app_type] => utility [patent_app_number] => 18/593817 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/593817
Asynchronous release operations in a multiprocessor system Feb 29, 2024 Issued
Array ( [id] => 20195394 [patent_doc_number] => 20250272104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => SWITCHING A PREDICTED BRANCH TYPE FOLLOWING A MISPREDICTION OF A NUMBER OF LOOP ITERATIONS [patent_app_type] => utility [patent_app_number] => 18/588615 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18588615 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/588615
Switching a predicted branch type following a misprediction of a number of loop iterations Feb 26, 2024 Issued
Array ( [id] => 19334283 [patent_doc_number] => 20240248713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => VECTOR PROCESSOR PERFORMING VECTOR AND ELEMENT REDUCTION METHOD WITH SAME CIRCUIT STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/582614 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582614 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/582614
VECTOR PROCESSOR PERFORMING VECTOR AND ELEMENT REDUCTION METHOD WITH SAME CIRCUIT STRUCTURE Feb 19, 2024 Abandoned
Array ( [id] => 19718826 [patent_doc_number] => 12204363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network [patent_app_type] => utility [patent_app_number] => 18/412846 [patent_app_country] => US [patent_app_date] => 2024-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 48 [patent_no_of_words] => 60845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412846 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/412846
System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network Jan 14, 2024 Issued
Array ( [id] => 19129219 [patent_doc_number] => 20240134572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => ALLOCATION OF MEMORY BY MAPPING REGISTERS REFERENCED BY DIFFERENT INSTANCES OF A TASK TO INDIVIDUAL LOGICAL MEMORIES [patent_app_type] => utility [patent_app_number] => 18/401558 [patent_app_country] => US [patent_app_date] => 2023-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401558 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401558
ALLOCATION OF MEMORY BY MAPPING REGISTERS REFERENCED BY DIFFERENT INSTANCES OF A TASK TO INDIVIDUAL LOGICAL MEMORIES Dec 30, 2023 Pending
Array ( [id] => 20070656 [patent_doc_number] => 20250208878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => ACCUMULATION APERTURES [patent_app_type] => utility [patent_app_number] => 18/390821 [patent_app_country] => US [patent_app_date] => 2023-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18390821 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/390821
ACCUMULATION APERTURES Dec 19, 2023 Pending
Array ( [id] => 20051997 [patent_doc_number] => 20250190219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => MAINTAINING APPROXIMATE UNIFORMITY OF AGING OF EQUIVALENT PROCESSING CIRCUITS IN A PIPELINE STAGE(S) IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/533711 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18533711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/533711
Maintaining approximate uniformity of aging of equivalent processing circuits in a pipeline stage(s) in a processor Dec 7, 2023 Issued
Array ( [id] => 19283780 [patent_doc_number] => 20240220256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => POLYMORPHIC TWO-DIMENSIONAL REGISTER FILE [patent_app_type] => utility [patent_app_number] => 18/525217 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18525217 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/525217
POLYMORPHIC TWO-DIMENSIONAL REGISTER FILE Nov 29, 2023 Abandoned
Array ( [id] => 19347319 [patent_doc_number] => 20240256282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => IN-ORDER PROCESSOR USING MULTIPLE-ISSUE SCHEME AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/516513 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516513 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/516513
IN-ORDER PROCESSOR USING MULTIPLE-ISSUE SCHEME AND METHOD OF OPERATING THE SAME Nov 20, 2023 Pending
Array ( [id] => 18941737 [patent_doc_number] => 20240036876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => PIPELINE PROTECTION FOR CPUS WITH SAVE AND RESTORE OF INTERMEDIATE RESULTS [patent_app_type] => utility [patent_app_number] => 18/487186 [patent_app_country] => US [patent_app_date] => 2023-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18487186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/487186
CPUs with capture queues to save and restore intermediate results and out-of-order results Oct 15, 2023 Issued
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