Search

Keith E. Vicary

Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
798
Issued Applications
429
Pending Applications
76
Abandoned Applications
310

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8735176 [patent_doc_number] => 20130080745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'FINE-GRAINED INSTRUCTION ENABLEMENT AT SUB-FUNCTION GRANULARITY' [patent_app_type] => utility [patent_app_number] => 13/681520 [patent_app_country] => US [patent_app_date] => 2012-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14833 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13681520 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/681520
Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers Nov 19, 2012 Issued
Array ( [id] => 8735469 [patent_doc_number] => 20130081038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'MULTIPROCESSOR COMPUTING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/680369 [patent_app_country] => US [patent_app_date] => 2012-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3454 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13680369 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/680369
MULTIPROCESSOR COMPUTING DEVICE Nov 18, 2012 Abandoned
Array ( [id] => 9465380 [patent_doc_number] => 20140129807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'APPROACH FOR EFFICIENT ARITHMETIC OPERATIONS' [patent_app_type] => utility [patent_app_number] => 13/671485 [patent_app_country] => US [patent_app_date] => 2012-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13671485 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/671485
Providing hints to an execution unit to prepare for predicted subsequent arithmetic operations Nov 6, 2012 Issued
Array ( [id] => 9578813 [patent_doc_number] => 08769249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Instructions with floating point control override' [patent_app_type] => utility [patent_app_number] => 13/670326 [patent_app_country] => US [patent_app_date] => 2012-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4714 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13670326 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/670326
Instructions with floating point control override Nov 5, 2012 Issued
Array ( [id] => 9398408 [patent_doc_number] => 20140095814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'Memory Renaming Mechanism in Microarchitecture' [patent_app_type] => utility [patent_app_number] => 13/631644 [patent_app_country] => US [patent_app_date] => 2012-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5140 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13631644 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/631644
Memory Renaming Mechanism in Microarchitecture Sep 27, 2012 Abandoned
Array ( [id] => 9089369 [patent_doc_number] => 08560815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Processing vectors using wrapping boolean instructions in the macroscalar architecture' [patent_app_type] => utility [patent_app_number] => 13/628857 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 49565 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13628857 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/628857
Processing vectors using wrapping boolean instructions in the macroscalar architecture Sep 26, 2012 Issued
Array ( [id] => 9143423 [patent_doc_number] => 08583904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Processing vectors using wrapping negation instructions in the macroscalar architecture' [patent_app_type] => utility [patent_app_number] => 13/628781 [patent_app_country] => US [patent_app_date] => 2012-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 49639 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13628781 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/628781
Processing vectors using wrapping negation instructions in the macroscalar architecture Sep 26, 2012 Issued
Array ( [id] => 9029609 [patent_doc_number] => 08539205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Processing vectors using wrapping multiply and divide instructions in the macroscalar architecture' [patent_app_type] => utility [patent_app_number] => 13/625131 [patent_app_country] => US [patent_app_date] => 2012-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 49634 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13625131 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/625131
Processing vectors using wrapping multiply and divide instructions in the macroscalar architecture Sep 23, 2012 Issued
Array ( [id] => 8650564 [patent_doc_number] => 20130036293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-07 [patent_title] => 'PROCESSING VECTORS USING WRAPPING MINIMA AND MAXIMA INSTRUCTIONS IN THE MACROSCALAR ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/625164 [patent_app_country] => US [patent_app_date] => 2012-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 49446 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13625164 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/625164
Processing vectors using wrapping minima and maxima instructions in the macroscalar architecture Sep 23, 2012 Issued
Array ( [id] => 8619357 [patent_doc_number] => 20130024669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'PROCESSING VECTORS USING WRAPPING SHIFT INSTRUCTIONS IN THE MACROSCALAR ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/625097 [patent_app_country] => US [patent_app_date] => 2012-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 49430 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13625097 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/625097
Processing vectors using wrapping shift instructions in the macroscalar architecture Sep 23, 2012 Issued
Array ( [id] => 8588602 [patent_doc_number] => 20130007422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'PROCESSING VECTORS USING WRAPPING ADD AND SUBTRACT INSTRUCTIONS IN THE MACROSCALAR ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/610299 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 49770 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610299 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/610299
Processing vectors using wrapping add and subtract instructions in the macroscalar architecture Sep 10, 2012 Issued
Array ( [id] => 8710183 [patent_doc_number] => 20130067472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'ORGANIZATION OF HETEROGENEOUS ENTITIES INTO SYSTEM RESOURCE GROUPS FOR DEFINING POLICY MANAGEMENT FRAMEWORK IN VIRTUAL CLUSTER MANAGED SYSTEMS ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 13/610851 [patent_app_country] => US [patent_app_date] => 2012-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610851 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/610851
Organization of virtual heterogeneous entities into system resource groups for defining policy management framework in a managed systems environment Sep 10, 2012 Issued
Array ( [id] => 8568748 [patent_doc_number] => 20120331319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'SYSTEM AND METHOD FOR POWER OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 13/604496 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7958 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604496 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604496
SYSTEM AND METHOD FOR POWER OPTIMIZATION Sep 4, 2012 Abandoned
Array ( [id] => 8568704 [patent_doc_number] => 20120331275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'SYSTEM AND METHOD FOR POWER OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 13/604390 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7958 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604390 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604390
SYSTEM AND METHOD FOR POWER OPTIMIZATION Sep 4, 2012 Abandoned
Array ( [id] => 8632837 [patent_doc_number] => 08364936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies' [patent_app_type] => utility [patent_app_number] => 13/557725 [patent_app_country] => US [patent_app_date] => 2012-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6896 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13557725 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/557725
Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies Jul 24, 2012 Issued
Array ( [id] => 8479402 [patent_doc_number] => 20120278809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'LOCK BASED MOVING OF THREADS IN A SHARED PROCESSOR PARTITIONING ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 13/544958 [patent_app_country] => US [patent_app_date] => 2012-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6370 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13544958 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/544958
LOCK BASED MOVING OF THREADS IN A SHARED PROCESSOR PARTITIONING ENVIRONMENT Jul 8, 2012 Abandoned
Array ( [id] => 11816777 [patent_doc_number] => 09720726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Multi-dimensional thread grouping for multiple processors' [patent_app_type] => utility [patent_app_number] => 13/534900 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 12782 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13534900 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/534900
Multi-dimensional thread grouping for multiple processors Jun 26, 2012 Issued
Array ( [id] => 8407843 [patent_doc_number] => 20120239911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'VALUE CHECK INSTRUCTION FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 13/484709 [patent_app_country] => US [patent_app_date] => 2012-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7334 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13484709 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/484709
Instruction for comparing active vector elements to preceding active elements to determine value differences May 30, 2012 Issued
Array ( [id] => 8407841 [patent_doc_number] => 20120239910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'CONDITIONAL EXTRACT INSTRUCTION FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 13/484666 [patent_app_country] => US [patent_app_date] => 2012-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7050 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13484666 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/484666
CONDITIONAL EXTRACT INSTRUCTION FOR PROCESSING VECTORS May 30, 2012 Abandoned
Array ( [id] => 8395489 [patent_doc_number] => 20120233332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'Resource Property Aggregation in a Multi-Provider System' [patent_app_type] => utility [patent_app_number] => 13/479436 [patent_app_country] => US [patent_app_date] => 2012-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6442 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13479436 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/479436
Resource Property Aggregation in a Multi-Provider System May 23, 2012 Abandoned
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