Search

Keith E. Vicary

Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
798
Issued Applications
429
Pending Applications
76
Abandoned Applications
310

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8372440 [patent_doc_number] => 20120221837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'RUNNING MULTIPLY-ACCUMULATE INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 13/463454 [patent_app_country] => US [patent_app_date] => 2012-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10579 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463454 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/463454
Running multiply-accumulate instructions for processing vectors May 2, 2012 Issued
Array ( [id] => 8349192 [patent_doc_number] => 20120210099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'RUNNING UNARY OPERATION INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 13/456371 [patent_app_country] => US [patent_app_date] => 2012-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 50145 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13456371 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/456371
Running unary operation instructions for processing vectors Apr 25, 2012 Issued
Array ( [id] => 12213865 [patent_doc_number] => 09910674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Data processor with extended instruction code space including a prohibition combination pattern as a separate instruction' [patent_app_type] => utility [patent_app_number] => 14/113058 [patent_app_country] => US [patent_app_date] => 2012-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 21028 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14113058 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/113058
Data processor with extended instruction code space including a prohibition combination pattern as a separate instruction Apr 9, 2012 Issued
Array ( [id] => 9604823 [patent_doc_number] => 20140201505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/997837 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997837 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997837
PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR Mar 29, 2012 Abandoned
Array ( [id] => 9618217 [patent_doc_number] => 20140208074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'INSTRUCTION SCHEDULING FOR A MULTI-STRAND OUT-OF-ORDER PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/993552 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6522 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993552 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993552
INSTRUCTION SCHEDULING FOR A MULTI-STRAND OUT-OF-ORDER PROCESSOR Mar 29, 2012 Abandoned
Array ( [id] => 8303295 [patent_doc_number] => 20120185853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'Virtual Input-Output Connections for Machine Virtualization' [patent_app_type] => utility [patent_app_number] => 13/431995 [patent_app_country] => US [patent_app_date] => 2012-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5150 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431995 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/431995
Virtual input-output connections for machine virtualization Mar 27, 2012 Issued
Array ( [id] => 8775645 [patent_doc_number] => 08429621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Component lock tracing by associating component type parameters with particular lock instances' [patent_app_type] => utility [patent_app_number] => 13/431382 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3413 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431382 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/431382
Component lock tracing by associating component type parameters with particular lock instances Mar 26, 2012 Issued
Array ( [id] => 9224947 [patent_doc_number] => 20140019722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'PROCESSOR AND INSTRUCTION PROCESSING METHOD OF PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/006950 [patent_app_country] => US [patent_app_date] => 2012-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 6487 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14006950 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/006950
PROCESSOR AND INSTRUCTION PROCESSING METHOD OF PROCESSOR Feb 23, 2012 Abandoned
Array ( [id] => 14298571 [patent_doc_number] => 10289412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Floating point constant generation instruction [patent_app_type] => utility [patent_app_number] => 13/369693 [patent_app_country] => US [patent_app_date] => 2012-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3618 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13369693 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/369693
Floating point constant generation instruction Feb 8, 2012 Issued
Array ( [id] => 14490201 [patent_doc_number] => 10331891 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Branch target computation in secure start-up using an integrity datum and an adjustment datum [patent_app_type] => utility [patent_app_number] => 13/366721 [patent_app_country] => US [patent_app_date] => 2012-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13366721 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/366721
Branch target computation in secure start-up using an integrity datum and an adjustment datum Feb 5, 2012 Issued
Array ( [id] => 8383419 [patent_doc_number] => 20120227045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-06 [patent_title] => 'METHOD, APPARATUS, AND SYSTEM FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND RESTORING' [patent_app_type] => utility [patent_app_number] => 13/365104 [patent_app_country] => US [patent_app_date] => 2012-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 23139 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13365104 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/365104
METHOD, APPARATUS, AND SYSTEM FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND RESTORING Feb 1, 2012 Abandoned
Array ( [id] => 10922165 [patent_doc_number] => 20140325185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'Method for Operating a Processor' [patent_app_type] => utility [patent_app_number] => 14/364138 [patent_app_country] => US [patent_app_date] => 2012-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5226 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14364138 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/364138
Method for Operating a Processor Jan 30, 2012 Abandoned
Array ( [id] => 9645032 [patent_doc_number] => 20140223145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'Configurable Reduced Instruction Set Core' [patent_app_type] => utility [patent_app_number] => 13/992797 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2813 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13992797 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/992797
Configurable Reduced Instruction Set Core Dec 29, 2011 Abandoned
Array ( [id] => 9722984 [patent_doc_number] => 20140258685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'Using Reduced Instruction Set Cores' [patent_app_type] => utility [patent_app_number] => 13/992856 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1890 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13992856 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/992856
Using Reduced Instruction Set Cores Dec 29, 2011 Abandoned
Array ( [id] => 8906382 [patent_doc_number] => 20130173885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-04 [patent_title] => 'Processor and Methods of Adjusting a Branch Misprediction Recovery Mode' [patent_app_type] => utility [patent_app_number] => 13/341558 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13341558 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/341558
Processor and Methods of Adjusting a Branch Misprediction Recovery Mode Dec 29, 2011 Abandoned
Array ( [id] => 9372461 [patent_doc_number] => 20140082334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'Encoding to Increase Instruction Set Density' [patent_app_type] => utility [patent_app_number] => 13/992722 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2480 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13992722 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/992722
Encoding to Increase Instruction Set Density Dec 29, 2011 Abandoned
Array ( [id] => 9193390 [patent_doc_number] => 20130332705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTWARE AT CODE REGION GRANULARITY' [patent_app_type] => utility [patent_app_number] => 13/993054 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5128 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993054 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993054
Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region Dec 28, 2011 Issued
Array ( [id] => 9200374 [patent_doc_number] => 20130339689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'LATER STAGE READ PORT REDUCTION' [patent_app_type] => utility [patent_app_number] => 13/993546 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6551 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993546 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993546
LATER STAGE READ PORT REDUCTION Dec 28, 2011 Abandoned
Array ( [id] => 9224948 [patent_doc_number] => 20140019723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'BINARY TRANSLATION IN ASYMMETRIC MULTIPROCESSOR SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/993042 [patent_app_country] => US [patent_app_date] => 2011-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993042 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993042
BINARY TRANSLATION IN ASYMMETRIC MULTIPROCESSOR SYSTEM Dec 27, 2011 Abandoned
Array ( [id] => 9571611 [patent_doc_number] => 20140189323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'APPARATUS AND METHOD FOR PROPAGATING CONDITIONALLY EVALUATED VALUES IN SIMD/VECTOR EXECUTION' [patent_app_type] => utility [patent_app_number] => 13/997183 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14818 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997183 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997183
Apparatus and method for propagating conditionally evaluated values in SIMD/vector execution using an input mask register Dec 22, 2011 Issued
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