Search

Keith E. Vicary

Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
798
Issued Applications
429
Pending Applications
76
Abandoned Applications
310

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9213909 [patent_doc_number] => 20140013086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'ADDITION INSTRUCTIONS WITH INDEPENDENT CARRY CHAINS' [patent_app_type] => utility [patent_app_number] => 13/993483 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7254 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993483 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993483
Addition instructions with independent carry chains Dec 21, 2011 Issued
Array ( [id] => 9341443 [patent_doc_number] => 20140068227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR EXTRACTING A WRITEMASK FROM A REGISTER' [patent_app_type] => utility [patent_app_number] => 13/993519 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10615 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993519 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993519
SYSTEMS, APPARATUSES, AND METHODS FOR EXTRACTING A WRITEMASK FROM A REGISTER Dec 21, 2011 Abandoned
Array ( [id] => 11577525 [patent_doc_number] => 09632786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Instruction set architecture with extended register addressing using one or more primary opcode bits' [patent_app_type] => utility [patent_app_number] => 13/330804 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 11095 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13330804 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/330804
Instruction set architecture with extended register addressing using one or more primary opcode bits Dec 19, 2011 Issued
Array ( [id] => 11577518 [patent_doc_number] => 09632779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Instruction predication using instruction filtering' [patent_app_type] => utility [patent_app_number] => 13/329575 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 11219 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13329575 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/329575
Instruction predication using instruction filtering Dec 18, 2011 Issued
Array ( [id] => 8886500 [patent_doc_number] => 20130159684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'BATCHED REPLAYS OF DIVERGENT OPERATIONS' [patent_app_type] => utility [patent_app_number] => 13/329066 [patent_app_country] => US [patent_app_date] => 2011-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13329066 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/329066
Batched replays of divergent operations Dec 15, 2011 Issued
Array ( [id] => 13130203 [patent_doc_number] => 10083032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => System, apparatus and method for generating a loop alignment count or a loop alignment mask [patent_app_type] => utility [patent_app_number] => 13/993321 [patent_app_country] => US [patent_app_date] => 2011-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 11880 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993321 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993321
System, apparatus and method for generating a loop alignment count or a loop alignment mask Dec 13, 2011 Issued
Array ( [id] => 9571583 [patent_doc_number] => 20140189296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'SYSTEM, APPARATUS AND METHOD FOR LOOP REMAINDER MASK INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 13/993323 [patent_app_country] => US [patent_app_date] => 2011-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12270 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993323 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993323
SYSTEM, APPARATUS AND METHOD FOR LOOP REMAINDER MASK INSTRUCTION Dec 13, 2011 Abandoned
Array ( [id] => 7770350 [patent_doc_number] => 20120036338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'FACILITATING PROCESSING IN A COMPUTING ENVIRONMENT USING AN EXTENDED DRAIN INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 13/273320 [patent_app_country] => US [patent_app_date] => 2011-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6483 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20120036338.pdf [firstpage_image] =>[orig_patent_app_number] => 13273320 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/273320
Facilitating processing in a computing environment using an extended drain instruction Oct 13, 2011 Issued
Array ( [id] => 8741131 [patent_doc_number] => 08412917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Data exchange and communication between execution units in a parallel processor' [patent_app_type] => utility [patent_app_number] => 13/237646 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 7223 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13237646 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237646
Data exchange and communication between execution units in a parallel processor Sep 19, 2011 Issued
Array ( [id] => 11830595 [patent_doc_number] => 09727336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers' [patent_app_type] => utility [patent_app_number] => 13/234785 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14954 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13234785 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/234785
Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers Sep 15, 2011 Issued
Array ( [id] => 10890600 [patent_doc_number] => 08914613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits' [patent_app_type] => utility [patent_app_number] => 13/219418 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5281 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13219418 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219418
Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits Aug 25, 2011 Issued
Array ( [id] => 15386847 [patent_doc_number] => 10534608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Local computation logic embedded in a register file to accelerate programs [patent_app_type] => utility [patent_app_number] => 13/211701 [patent_app_country] => US [patent_app_date] => 2011-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5142 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13211701 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/211701
Local computation logic embedded in a register file to accelerate programs Aug 16, 2011 Issued
Array ( [id] => 13212645 [patent_doc_number] => 10120692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Methods and apparatus for storage and translation of an entropy encoded instruction sequence to executable form [patent_app_type] => utility [patent_app_number] => 13/192916 [patent_app_country] => US [patent_app_date] => 2011-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7026 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13192916 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/192916
Methods and apparatus for storage and translation of an entropy encoded instruction sequence to executable form Jul 27, 2011 Issued
Array ( [id] => 13212645 [patent_doc_number] => 10120692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Methods and apparatus for storage and translation of an entropy encoded instruction sequence to executable form [patent_app_type] => utility [patent_app_number] => 13/192916 [patent_app_country] => US [patent_app_date] => 2011-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7026 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13192916 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/192916
Methods and apparatus for storage and translation of an entropy encoded instruction sequence to executable form Jul 27, 2011 Issued
Array ( [id] => 13212645 [patent_doc_number] => 10120692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Methods and apparatus for storage and translation of an entropy encoded instruction sequence to executable form [patent_app_type] => utility [patent_app_number] => 13/192916 [patent_app_country] => US [patent_app_date] => 2011-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7026 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13192916 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/192916
Methods and apparatus for storage and translation of an entropy encoded instruction sequence to executable form Jul 27, 2011 Issued
Array ( [id] => 13212645 [patent_doc_number] => 10120692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Methods and apparatus for storage and translation of an entropy encoded instruction sequence to executable form [patent_app_type] => utility [patent_app_number] => 13/192916 [patent_app_country] => US [patent_app_date] => 2011-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7026 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13192916 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/192916
Methods and apparatus for storage and translation of an entropy encoded instruction sequence to executable form Jul 27, 2011 Issued
Array ( [id] => 7562948 [patent_doc_number] => 20110276782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'RUNNING SUBTRACT AND RUNNING DIVIDE INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 13/188737 [patent_app_country] => US [patent_app_date] => 2011-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 42813 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20110276782.pdf [firstpage_image] =>[orig_patent_app_number] => 13188737 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/188737
Running subtract and running divide instructions for processing vectors Jul 21, 2011 Issued
Array ( [id] => 7588581 [patent_doc_number] => 20110283092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'GETFIRST AND ASSIGNLAST INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 13/189140 [patent_app_country] => US [patent_app_date] => 2011-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 37051 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20110283092.pdf [firstpage_image] =>[orig_patent_app_number] => 13189140 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/189140
GETFIRST AND ASSIGNLAST INSTRUCTIONS FOR PROCESSING VECTORS Jul 21, 2011 Abandoned
Array ( [id] => 6020317 [patent_doc_number] => 20110225398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'ADVANCED PROCESSOR SCHEDULING IN A MULTITHREADED SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/115012 [patent_app_country] => US [patent_app_date] => 2011-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13433 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225398.pdf [firstpage_image] =>[orig_patent_app_number] => 13115012 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/115012
ADVANCED PROCESSOR SCHEDULING IN A MULTITHREADED SYSTEM May 23, 2011 Abandoned
Array ( [id] => 8804886 [patent_doc_number] => 08443169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processor' [patent_app_type] => utility [patent_app_number] => 12/932542 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 54 [patent_no_of_words] => 26416 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12932542 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/932542
Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processor Feb 27, 2011 Issued
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