Search

Keith E. Vicary

Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
798
Issued Applications
429
Pending Applications
76
Abandoned Applications
310

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8058997 [patent_doc_number] => 20120079233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'VECTOR LOGICAL REDUCTION OPERATION IMPLEMENTED ON A SEMICONDUCTOR CHIP' [patent_app_type] => utility [patent_app_number] => 12/890485 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20120079233.pdf [firstpage_image] =>[orig_patent_app_number] => 12890485 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/890485
Vector logical reduction operation implemented using swizzling on a semiconductor chip Sep 23, 2010 Issued
Array ( [id] => 9029608 [patent_doc_number] => 08539206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Method and apparatus for universal logical operations utilizing value indexing' [patent_app_type] => utility [patent_app_number] => 12/890571 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4644 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12890571 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/890571
Method and apparatus for universal logical operations utilizing value indexing Sep 23, 2010 Issued
Array ( [id] => 6634014 [patent_doc_number] => 20100325398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'RUNNING-MIN AND RUNNING-MAX INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 12/873043 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 38713 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0325/20100325398.pdf [firstpage_image] =>[orig_patent_app_number] => 12873043 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/873043
Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector Aug 30, 2010 Issued
Array ( [id] => 7714172 [patent_doc_number] => 20120005463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'BRANCH TRACE HISTORY COMPRESSION' [patent_app_type] => utility [patent_app_number] => 12/827916 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8604 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20120005463.pdf [firstpage_image] =>[orig_patent_app_number] => 12827916 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/827916
Branch trace history compression Jun 29, 2010 Issued
Array ( [id] => 9089368 [patent_doc_number] => 08560816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'System and method for performing incremental register checkpointing in transactional memory' [patent_app_type] => utility [patent_app_number] => 12/827842 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 14107 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12827842 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/827842
System and method for performing incremental register checkpointing in transactional memory Jun 29, 2010 Issued
Array ( [id] => 7671497 [patent_doc_number] => 20110320766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'APPARATUS, METHOD, AND SYSTEM FOR IMPROVING POWER, PERFORMANCE EFFICIENCY BY COUPLING A FIRST CORE TYPE WITH A SECOND CORE TYPE' [patent_app_type] => utility [patent_app_number] => 12/826107 [patent_app_country] => US [patent_app_date] => 2010-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11666 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12826107 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/826107
APPARATUS, METHOD, AND SYSTEM FOR IMPROVING POWER, PERFORMANCE EFFICIENCY BY COUPLING A FIRST CORE TYPE WITH A SECOND CORE TYPE Jun 28, 2010 Abandoned
Array ( [id] => 6362737 [patent_doc_number] => 20100332798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'Digital Processor and Method' [patent_app_type] => utility [patent_app_number] => 12/825402 [patent_app_country] => US [patent_app_date] => 2010-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5430 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0332/20100332798.pdf [firstpage_image] =>[orig_patent_app_number] => 12825402 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/825402
Digital Processor and Method Jun 28, 2010 Abandoned
Array ( [id] => 7671512 [patent_doc_number] => 20110320781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'DYNAMIC DATA SYNCHRONIZATION IN THREAD-LEVEL SPECULATION' [patent_app_type] => utility [patent_app_number] => 12/826287 [patent_app_country] => US [patent_app_date] => 2010-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1719 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12826287 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/826287
DYNAMIC DATA SYNCHRONIZATION IN THREAD-LEVEL SPECULATION Jun 28, 2010 Abandoned
Array ( [id] => 6197999 [patent_doc_number] => 20110029757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'STREAM PROCESSOR AND TASK MANAGEMENT METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/825868 [patent_app_country] => US [patent_app_date] => 2010-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5584 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20110029757.pdf [firstpage_image] =>[orig_patent_app_number] => 12825868 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/825868
STREAM PROCESSOR AND TASK MANAGEMENT METHOD THEREOF Jun 28, 2010 Abandoned
Array ( [id] => 6362755 [patent_doc_number] => 20100332800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'Instruction control device, instruction control method, and processor' [patent_app_type] => utility [patent_app_number] => 12/801871 [patent_app_country] => US [patent_app_date] => 2010-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8842 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0332/20100332800.pdf [firstpage_image] =>[orig_patent_app_number] => 12801871 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/801871
Instruction control device, instruction control method, and processor Jun 28, 2010 Abandoned
Array ( [id] => 7671511 [patent_doc_number] => 20110320780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'HYBRID COMPARE AND SWAP/PERFORM LOCKED OPERATION QUEUE ALGORITHM' [patent_app_type] => utility [patent_app_number] => 12/825242 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12825242 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/825242
Hybrid compare and swap/perform locked operation queue algorithm Jun 27, 2010 Issued
Array ( [id] => 10637384 [patent_doc_number] => 09354887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Instruction buffer bypass of target instruction in response to partial flush' [patent_app_type] => utility [patent_app_number] => 12/824812 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9051 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12824812 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/824812
Instruction buffer bypass of target instruction in response to partial flush Jun 27, 2010 Issued
Array ( [id] => 7671496 [patent_doc_number] => 20110320765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'VARIABLE WIDTH VECTOR INSTRUCTION PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/825328 [patent_app_country] => US [patent_app_date] => 2010-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6475 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12825328 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/825328
VARIABLE WIDTH VECTOR INSTRUCTION PROCESSOR Jun 27, 2010 Abandoned
Array ( [id] => 6363882 [patent_doc_number] => 20100250904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'METHODS AND PROCESSOR-RELATED MEDIA TO PERFORM RAPID RETURNS FROM SUBROUTINES IN MICROPROCESSORS AND MICROCONTROLLERS' [patent_app_type] => utility [patent_app_number] => 12/795582 [patent_app_country] => US [patent_app_date] => 2010-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20100250904.pdf [firstpage_image] =>[orig_patent_app_number] => 12795582 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/795582
Method for performing a return operation in parallel with setting status flags based on a return value register test Jun 6, 2010 Issued
Array ( [id] => 5940028 [patent_doc_number] => 20110213950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'System and Method for Power Optimization' [patent_app_type] => utility [patent_app_number] => 12/787359 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7885 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20110213950.pdf [firstpage_image] =>[orig_patent_app_number] => 12787359 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787359
System and Method for Power Optimization May 24, 2010 Abandoned
Array ( [id] => 5940025 [patent_doc_number] => 20110213947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'System and Method for Power Optimization' [patent_app_type] => utility [patent_app_number] => 12/787360 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7885 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20110213947.pdf [firstpage_image] =>[orig_patent_app_number] => 12787360 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787360
System and Method for Power Optimization May 24, 2010 Abandoned
Array ( [id] => 5940125 [patent_doc_number] => 20110213998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'System and Method for Power Optimization' [patent_app_type] => utility [patent_app_number] => 12/787361 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7885 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20110213998.pdf [firstpage_image] =>[orig_patent_app_number] => 12787361 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787361
System and Method for Power Optimization May 24, 2010 Abandoned
Array ( [id] => 6584732 [patent_doc_number] => 20100235608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'METHOD AND APPARATUS FOR GAME PHYSICS CONCURRENT COMPUTATIONS' [patent_app_type] => utility [patent_app_number] => 12/785837 [patent_app_country] => US [patent_app_date] => 2010-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4992 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20100235608.pdf [firstpage_image] =>[orig_patent_app_number] => 12785837 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/785837
METHOD AND APPARATUS FOR GAME PHYSICS CONCURRENT COMPUTATIONS May 23, 2010 Abandoned
Array ( [id] => 6006087 [patent_doc_number] => 20110119472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'BRANCH PREDICTING DEVICE, BRANCH PREDICTING METHOD THEREOF, COMPILER, COMPILING METHOD THEREOF, AND MEDIUM FOR STORING BRANCH PREDICTING PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/001852 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10221 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20110119472.pdf [firstpage_image] =>[orig_patent_app_number] => 13001852 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/001852
Branch prediction using a leading value of a call stack storing function arguments May 18, 2010 Issued
Array ( [id] => 6643581 [patent_doc_number] => 20100312991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'Microprocessor with Compact Instruction Set Architecture' [patent_app_type] => utility [patent_app_number] => 12/748102 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18668 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0312/20100312991.pdf [firstpage_image] =>[orig_patent_app_number] => 12748102 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/748102
Microprocessor with Compact Instruction Set Architecture Mar 25, 2010 Abandoned
Menu