Keith E. Vicary

Array ( [id] => 5976649 [patent_doc_number] => 20110154111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'Memory Based Hardware Breakpoints' [patent_app_type] => utility [patent_app_number] => 12/962207 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5338 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20110154111.pdf [firstpage_image] =>[orig_patent_app_number] => 12962207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8229969 [patent_doc_number] => 20120144171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'Mechanism for Detection and Measurement of Hardware-Based Processor Latency' [patent_app_type] => utility [patent_app_number] => 12/962453 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12962453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8229911 [patent_doc_number] => 20120144120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'PROGRAMMABLE ATOMIC MEMORY USING HARDWARE VALIDATION AGENT' [patent_app_type] => utility [patent_app_number] => 12/961829 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9204 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12961829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9156748 [patent_doc_number] => 08589661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Odd and even start bit vectors' [patent_app_type] => utility [patent_app_number] => 12/962113 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3881 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12962113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8229967 [patent_doc_number] => 20120144175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'METHOD AND APPARATUS FOR AN ENHANCED SPEED UNIFIED SCHEDULER UTILIZING OPTYPES FOR COMPACT LOGIC' [patent_app_type] => utility [patent_app_number] => 12/958604 [patent_app_country] => US [patent_app_date] => 2010-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8092 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12958604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8229965 [patent_doc_number] => 20120144174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'MULTIFLOW METHOD AND APPARATUS FOR OPERATION FUSION' [patent_app_type] => utility [patent_app_number] => 12/957699 [patent_app_country] => US [patent_app_date] => 2010-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3601 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12957699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8229966 [patent_doc_number] => 20120144173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'UNIFIED SCHEDULER FOR A PROCESSOR MULTI-PIPELINE EXECUTION UNIT AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/957754 [patent_app_country] => US [patent_app_date] => 2010-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8756 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12957754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6217620 [patent_doc_number] => 20110138155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'VECTOR COMPUTER AND INSTRUCTION CONTROL METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 12/957913 [patent_app_country] => US [patent_app_date] => 2010-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7315 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20110138155.pdf [firstpage_image] =>[orig_patent_app_number] => 12957913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8109313 [patent_doc_number] => 08156311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => 'Interconnection networks and methods of construction thereof for efficiently sharing memory and processing in a multiprocessor wherein connections are made according to adjacency of nodes in a dimension' [patent_app_type] => utility [patent_app_number] => 12/927837 [patent_app_country] => US [patent_app_date] => 2010-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 11858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/156/08156311.pdf [firstpage_image] =>[orig_patent_app_number] => 12927837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5956772 [patent_doc_number] => 20110035568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'SELECT FIRST AND SELECT LAST INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 12/907471 [patent_app_country] => US [patent_app_date] => 2010-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 36397 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20110035568.pdf [firstpage_image] =>[orig_patent_app_number] => 12907471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9348092 [patent_doc_number] => 08667255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Measuring runtime coverage of architectural events of a microprocessor' [patent_app_type] => utility [patent_app_number] => 12/895034 [patent_app_country] => US [patent_app_date] => 2010-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6160 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12895034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6125343 [patent_doc_number] => 20110078413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'ARITHMETIC PROCESSING UNIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND ARITHMETIC PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 12/892128 [patent_app_country] => US [patent_app_date] => 2010-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4412 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20110078413.pdf [firstpage_image] =>[orig_patent_app_number] => 12892128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14614677 [patent_doc_number] => 10360039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Predicted instruction execution in parallel processors with reduced per-thread state information including choosing a minimum or maximum of two operands based on a predicate value [patent_app_type] => utility [patent_app_number] => 12/891629 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9060 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12891629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8059047 [patent_doc_number] => 20120079255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'INDIRECT BRANCH PREDICTION BASED ON BRANCH TARGET BUFFER HYSTERESIS' [patent_app_type] => utility [patent_app_number] => 12/890651 [patent_app_country] => US [patent_app_date] => 2010-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20120079255.pdf [firstpage_image] =>[orig_patent_app_number] => 12890651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11752265 [patent_doc_number] => 09710277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Processor power management based on class and content of instructions' [patent_app_type] => utility [patent_app_number] => 12/890574 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6057 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12890574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9029608 [patent_doc_number] => 08539206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Method and apparatus for universal logical operations utilizing value indexing' [patent_app_type] => utility [patent_app_number] => 12/890571 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4644 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12890571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8058997 [patent_doc_number] => 20120079233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'VECTOR LOGICAL REDUCTION OPERATION IMPLEMENTED ON A SEMICONDUCTOR CHIP' [patent_app_type] => utility [patent_app_number] => 12/890485 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20120079233.pdf [firstpage_image] =>[orig_patent_app_number] => 12890485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6634014 [patent_doc_number] => 20100325398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'RUNNING-MIN AND RUNNING-MAX INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 12/873043 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 38713 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0325/20100325398.pdf [firstpage_image] =>[orig_patent_app_number] => 12873043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7714172 [patent_doc_number] => 20120005463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'BRANCH TRACE HISTORY COMPRESSION' [patent_app_type] => utility [patent_app_number] => 12/827916 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8604 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20120005463.pdf [firstpage_image] =>[orig_patent_app_number] => 12827916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9089368 [patent_doc_number] => 08560816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'System and method for performing incremental register checkpointing in transactional memory' [patent_app_type] => utility [patent_app_number] => 12/827842 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 14107 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12827842 [rel_patent_id] =>[rel_patent_doc_number] =>)