
Keith E. Vicary
Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2182, 2183 |
| Total Applications | 798 |
| Issued Applications | 429 |
| Pending Applications | 76 |
| Abandoned Applications | 310 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8058997
[patent_doc_number] => 20120079233
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-29
[patent_title] => 'VECTOR LOGICAL REDUCTION OPERATION IMPLEMENTED ON A SEMICONDUCTOR CHIP'
[patent_app_type] => utility
[patent_app_number] => 12/890485
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/890485 | Vector logical reduction operation implemented using swizzling on a semiconductor chip | Sep 23, 2010 | Issued |
Array
(
[id] => 9029608
[patent_doc_number] => 08539206
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[patent_kind] => B2
[patent_issue_date] => 2013-09-17
[patent_title] => 'Method and apparatus for universal logical operations utilizing value indexing'
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Array
(
[id] => 6634014
[patent_doc_number] => 20100325398
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-23
[patent_title] => 'RUNNING-MIN AND RUNNING-MAX INSTRUCTIONS FOR PROCESSING VECTORS'
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[patent_app_date] => 2010-08-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/873043 | Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector | Aug 30, 2010 | Issued |
Array
(
[id] => 7714172
[patent_doc_number] => 20120005463
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[patent_title] => 'BRANCH TRACE HISTORY COMPRESSION'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2010-06-30
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/827916 | Branch trace history compression | Jun 29, 2010 | Issued |
Array
(
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Array
(
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[patent_doc_number] => 20110320766
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[patent_issue_date] => 2011-12-29
[patent_title] => 'APPARATUS, METHOD, AND SYSTEM FOR IMPROVING POWER, PERFORMANCE EFFICIENCY BY COUPLING A FIRST CORE TYPE WITH A SECOND CORE TYPE'
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Array
(
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[patent_title] => 'Digital Processor and Method'
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Array
(
[id] => 7671512
[patent_doc_number] => 20110320781
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[patent_kind] => A1
[patent_issue_date] => 2011-12-29
[patent_title] => 'DYNAMIC DATA SYNCHRONIZATION IN THREAD-LEVEL SPECULATION'
[patent_app_type] => utility
[patent_app_number] => 12/826287
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Array
(
[id] => 6197999
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[patent_title] => 'STREAM PROCESSOR AND TASK MANAGEMENT METHOD THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/825868 | STREAM PROCESSOR AND TASK MANAGEMENT METHOD THEREOF | Jun 28, 2010 | Abandoned |
Array
(
[id] => 6362755
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[patent_kind] => A1
[patent_issue_date] => 2010-12-30
[patent_title] => 'Instruction control device, instruction control method, and processor'
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Array
(
[id] => 7671511
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[patent_issue_date] => 2011-12-29
[patent_title] => 'HYBRID COMPARE AND SWAP/PERFORM LOCKED OPERATION QUEUE ALGORITHM'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/825242 | Hybrid compare and swap/perform locked operation queue algorithm | Jun 27, 2010 | Issued |
Array
(
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Array
(
[id] => 7671496
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[patent_title] => 'VARIABLE WIDTH VECTOR INSTRUCTION PROCESSOR'
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Array
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[patent_title] => 'METHODS AND PROCESSOR-RELATED MEDIA TO PERFORM RAPID RETURNS FROM SUBROUTINES IN MICROPROCESSORS AND MICROCONTROLLERS'
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/001852 | Branch prediction using a leading value of a call stack storing function arguments | May 18, 2010 | Issued |
Array
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