Search

Keith E. Vicary

Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
798
Issued Applications
429
Pending Applications
76
Abandoned Applications
310

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6478943 [patent_doc_number] => 20100191942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'Information processor and control method' [patent_app_type] => utility [patent_app_number] => 12/659896 [patent_app_country] => US [patent_app_date] => 2010-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11592 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20100191942.pdf [firstpage_image] =>[orig_patent_app_number] => 12659896 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659896
Information processing apparatus for inhibiting instructions, saving and restoring internal information in response to abnormality in redundant processor system Mar 23, 2010 Issued
Array ( [id] => 6363910 [patent_doc_number] => 20100250906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'Obfuscation' [patent_app_type] => utility [patent_app_number] => 12/721058 [patent_app_country] => US [patent_app_date] => 2010-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20100250906.pdf [firstpage_image] =>[orig_patent_app_number] => 12721058 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/721058
Obfuscation Mar 9, 2010 Abandoned
Array ( [id] => 7746271 [patent_doc_number] => 08108628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Processor instruction used to perform a matrix test to generate a memory-related trap' [patent_app_type] => utility [patent_app_number] => 12/658669 [patent_app_country] => US [patent_app_date] => 2010-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4623 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/108/08108628.pdf [firstpage_image] =>[orig_patent_app_number] => 12658669 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/658669
Processor instruction used to perform a matrix test to generate a memory-related trap Feb 11, 2010 Issued
Array ( [id] => 6413602 [patent_doc_number] => 20100306509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'OUT-OF-ORDER EXECUTION MICROPROCESSOR WITH REDUCED STORE COLLISION LOAD REPLAY REDUCTION' [patent_app_type] => utility [patent_app_number] => 12/604863 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20100306509.pdf [firstpage_image] =>[orig_patent_app_number] => 12604863 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/604863
OUT-OF-ORDER EXECUTION MICROPROCESSOR WITH REDUCED STORE COLLISION LOAD REPLAY REDUCTION Oct 22, 2009 Abandoned
Array ( [id] => 6491261 [patent_doc_number] => 20100042796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'Updation of Disk Images to Facilitate Virtualized Workspaces in a Virtual Computing Environment' [patent_app_type] => utility [patent_app_number] => 12/604662 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 19746 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20100042796.pdf [firstpage_image] =>[orig_patent_app_number] => 12604662 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/604662
Updation of Disk Images to Facilitate Virtualized Workspaces in a Virtual Computing Environment Oct 22, 2009 Abandoned
Array ( [id] => 9820876 [patent_doc_number] => 08930679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Out-of-order execution microprocessor with reduced store collision load replay by making an issuing of a load instruction dependent upon a dependee instruction of a store instruction' [patent_app_type] => utility [patent_app_number] => 12/604767 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 12882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12604767 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/604767
Out-of-order execution microprocessor with reduced store collision load replay by making an issuing of a load instruction dependent upon a dependee instruction of a store instruction Oct 22, 2009 Issued
Array ( [id] => 6493187 [patent_doc_number] => 20100042993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'Transportation of a Workspace from One Machine to Another in a Virtual Computing Environment without Installing Hardware' [patent_app_type] => utility [patent_app_number] => 12/603669 [patent_app_country] => US [patent_app_date] => 2009-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 19748 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20100042993.pdf [firstpage_image] =>[orig_patent_app_number] => 12603669 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/603669
Transportation of a Workspace from One Machine to Another in a Virtual Computing Environment without Installing Hardware Oct 21, 2009 Abandoned
Array ( [id] => 6492795 [patent_doc_number] => 20100042942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'Backup to Provide Hardware Agnostic Access to a Virtual Workspace Using Multiple Virtualization Dimensions' [patent_app_type] => utility [patent_app_number] => 12/582364 [patent_app_country] => US [patent_app_date] => 2009-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 19751 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20100042942.pdf [firstpage_image] =>[orig_patent_app_number] => 12582364 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/582364
Backup to Provide Hardware Agnostic Access to a Virtual Workspace Using Multiple Virtualization Dimensions Oct 19, 2009 Abandoned
Array ( [id] => 6493172 [patent_doc_number] => 20100042992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'Remote Access to Workspaces in a Virtual Computing Environment with Multiple Virtualization Dimensions' [patent_app_type] => utility [patent_app_number] => 12/582297 [patent_app_country] => US [patent_app_date] => 2009-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 19748 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20100042992.pdf [firstpage_image] =>[orig_patent_app_number] => 12582297 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/582297
Remote Access to Workspaces in a Virtual Computing Environment with Multiple Virtualization Dimensions Oct 19, 2009 Abandoned
Array ( [id] => 6628536 [patent_doc_number] => 20100100704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'Integrated circuit incorporating an array of interconnected processors executing a cycle-based program' [patent_app_type] => utility [patent_app_number] => 12/588413 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9122 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20100100704.pdf [firstpage_image] =>[orig_patent_app_number] => 12588413 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/588413
Integrated circuit incorporating an array of interconnected processors executing a cycle-based program Oct 13, 2009 Abandoned
Array ( [id] => 7684077 [patent_doc_number] => 20100122064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'METHOD FOR INCREASING CONFIGURATION RUNTIME OF TIME-SLICED CONFIGURATIONS' [patent_app_type] => utility [patent_app_number] => 12/571195 [patent_app_country] => US [patent_app_date] => 2009-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9198 [patent_no_of_claims] => 121 [patent_no_of_ind_claims] => 39 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20100122064.pdf [firstpage_image] =>[orig_patent_app_number] => 12571195 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/571195
METHOD FOR INCREASING CONFIGURATION RUNTIME OF TIME-SLICED CONFIGURATIONS Sep 29, 2009 Abandoned
Array ( [id] => 8810287 [patent_doc_number] => 08447954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Parallel pipelined vector reduction in a data processing system' [patent_app_type] => utility [patent_app_number] => 12/554074 [patent_app_country] => US [patent_app_date] => 2009-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4570 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12554074 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/554074
Parallel pipelined vector reduction in a data processing system Sep 3, 2009 Issued
Array ( [id] => 6073593 [patent_doc_number] => 20110047355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'Offset Based Register Address Indexing' [patent_app_type] => utility [patent_app_number] => 12/546071 [patent_app_country] => US [patent_app_date] => 2009-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4144 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20110047355.pdf [firstpage_image] =>[orig_patent_app_number] => 12546071 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/546071
Offset Based Register Address Indexing Aug 23, 2009 Abandoned
Array ( [id] => 6073599 [patent_doc_number] => 20110047358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'In-Data Path Tracking of Floating Point Exceptions and Store-Based Exception Indication' [patent_app_type] => utility [patent_app_number] => 12/543614 [patent_app_country] => US [patent_app_date] => 2009-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20110047358.pdf [firstpage_image] =>[orig_patent_app_number] => 12543614 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/543614
In-Data Path Tracking of Floating Point Exceptions and Store-Based Exception Indication Aug 18, 2009 Abandoned
Array ( [id] => 6073598 [patent_doc_number] => 20110047357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'Methods and Apparatus to Predict Non-Execution of Conditional Non-branching Instructions' [patent_app_type] => utility [patent_app_number] => 12/543847 [patent_app_country] => US [patent_app_date] => 2009-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8103 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20110047357.pdf [firstpage_image] =>[orig_patent_app_number] => 12543847 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/543847
Methods and Apparatus to Predict Non-Execution of Conditional Non-branching Instructions Aug 18, 2009 Abandoned
Array ( [id] => 8626957 [patent_doc_number] => 08359461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-22 [patent_title] => 'Running-shift instructions for processing vectors using a base value from a key element of an input vector' [patent_app_type] => utility [patent_app_number] => 12/541546 [patent_app_country] => US [patent_app_date] => 2009-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 38140 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12541546 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/541546
Running-shift instructions for processing vectors using a base value from a key element of an input vector Aug 13, 2009 Issued
Array ( [id] => 6616964 [patent_doc_number] => 20100049951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'RUNNING-AND, RUNNING-OR, RUNNING-XOR, AND RUNNING-MULTIPLY INSTRUCTIONS FOR PROCESSING VECTORS' [patent_app_type] => utility [patent_app_number] => 12/541526 [patent_app_country] => US [patent_app_date] => 2009-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 41299 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20100049951.pdf [firstpage_image] =>[orig_patent_app_number] => 12541526 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/541526
Running-AND, running-OR, running-XOR, and running-multiply instructions for processing vectors using a base value from a key element of an input vector Aug 13, 2009 Issued
Array ( [id] => 8626956 [patent_doc_number] => 08359460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-22 [patent_title] => 'Running-sum instructions for processing vectors using a base value from a key element of an input vector' [patent_app_type] => utility [patent_app_number] => 12/541505 [patent_app_country] => US [patent_app_date] => 2009-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 37588 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12541505 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/541505
Running-sum instructions for processing vectors using a base value from a key element of an input vector Aug 13, 2009 Issued
Array ( [id] => 6616905 [patent_doc_number] => 20100049948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'Serial flash semiconductor memory' [patent_app_type] => utility [patent_app_number] => 12/459590 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7387 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20100049948.pdf [firstpage_image] =>[orig_patent_app_number] => 12459590 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/459590
Serial flash semiconductor memory Jul 1, 2009 Abandoned
Array ( [id] => 6643650 [patent_doc_number] => 20100313000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'CONDITIONAL OPERATION IN AN INTERNAL PROCESSOR OF A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/478527 [patent_app_country] => US [patent_app_date] => 2009-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6339 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20100313000.pdf [firstpage_image] =>[orig_patent_app_number] => 12478527 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/478527
Conditional operation in an internal processor of a memory device Jun 3, 2009 Issued
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