Search

Keith E. Vicary

Examiner (ID: 15210)

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
804
Issued Applications
430
Pending Applications
77
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19530206 [patent_doc_number] => 20240354108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => MEMORY SAFETY USING TAG CHECKING INSTRUCTIONS AND ISLANDS OF TAGS IN LINE WITH BUCKETED DATA [patent_app_type] => utility [patent_app_number] => 18/478882 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18478882 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/478882
MEMORY SAFETY USING TAG CHECKING INSTRUCTIONS AND ISLANDS OF TAGS IN LINE WITH BUCKETED DATA Sep 28, 2023 Pending
Array ( [id] => 20087209 [patent_doc_number] => 20250217145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => TECHNIQUES FOR PIPELINING SINGLE THREAD INSTRUCTIONS TO IMPROVE EXECUTION TIME [patent_app_type] => utility [patent_app_number] => 18/550566 [patent_app_country] => US [patent_app_date] => 2023-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18550566 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/550566
TECHNIQUES FOR PIPELINING SINGLE THREAD INSTRUCTIONS TO IMPROVE EXECUTION TIME Sep 6, 2023 Pending
Array ( [id] => 19340725 [patent_doc_number] => 12050918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Coprocessor prefetcher [patent_app_type] => utility [patent_app_number] => 18/361244 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12497 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361244
Coprocessor prefetcher Jul 27, 2023 Issued
Array ( [id] => 20215035 [patent_doc_number] => 12411688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Gather buffer management for unaligned and gather load operations [patent_app_type] => utility [patent_app_number] => 18/225911 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5142 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225911 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225911
Gather buffer management for unaligned and gather load operations Jul 24, 2023 Issued
Array ( [id] => 19711374 [patent_doc_number] => 20250021516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => SINGLE INSTRUCTION MULTIPLE DISPATCHES FOR SHORT KERNELS IN A RECONFIGURABLE PARALLEL PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/220169 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220169 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/220169
Single instruction multiple dispatches for short kernels in a reconfigurable parallel processor Jul 9, 2023 Issued
Array ( [id] => 18904639 [patent_doc_number] => 20240020124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => Supporting Multiple Vector Lengths with Configurable Vector Register File [patent_app_type] => utility [patent_app_number] => 18/345007 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345007 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345007
Supporting Multiple Vector Lengths with Configurable Vector Register File Jun 29, 2023 Pending
Array ( [id] => 19971605 [patent_doc_number] => 12340220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Register mapping to map architectural registers to corresponding physical registers based on a mode indicating a register length [patent_app_type] => utility [patent_app_number] => 18/345164 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345164 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345164
Register mapping to map architectural registers to corresponding physical registers based on a mode indicating a register length Jun 29, 2023 Issued
Array ( [id] => 19686231 [patent_doc_number] => 20250004776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => INSTRUCTION FLOW REGULATOR FOR A PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 18/216201 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18216201 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/216201
INSTRUCTION FLOW REGULATOR FOR A PROCESSING UNIT Jun 28, 2023 Abandoned
Array ( [id] => 19686217 [patent_doc_number] => 20250004762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => BINARY CONVOLUTION INSTRUCTIONS FOR BINARY NEURAL NETWORK COMPUTATIONS [patent_app_type] => utility [patent_app_number] => 18/344091 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344091
BINARY CONVOLUTION INSTRUCTIONS FOR BINARY NEURAL NETWORK COMPUTATIONS Jun 28, 2023 Pending
Array ( [id] => 19660662 [patent_doc_number] => 20240427727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => HANDLING DYNAMIC TENSOR LENGTHS IN A RECONFIGURABLE PROCESSOR THAT INCLUDES MULTIPLE MEMORY UNITS [patent_app_type] => utility [patent_app_number] => 18/213598 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213598 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/213598
Handling dynamic tensor lengths in a reconfigurable processor that includes multiple memory units Jun 22, 2023 Issued
Array ( [id] => 18819511 [patent_doc_number] => 20230393851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => PROCESSING SYSTEM WITH INTEGRATED DOMAIN SPECIFIC ACCELERATORS [patent_app_type] => utility [patent_app_number] => 18/212128 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18212128 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/212128
PROCESSING SYSTEM WITH INTEGRATED DOMAIN SPECIFIC ACCELERATORS Jun 19, 2023 Pending
Array ( [id] => 18711379 [patent_doc_number] => 20230334008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => EXECUTION ENGINE FOR EXECUTING SINGLE ASSIGNMENT PROGRAMS WITH AFFINE DEPENDENCIES [patent_app_type] => utility [patent_app_number] => 18/211447 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211447 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/211447
EXECUTION ENGINE FOR EXECUTING SINGLE ASSIGNMENT PROGRAMS WITH AFFINE DEPENDENCIES Jun 18, 2023 Pending
Array ( [id] => 19219876 [patent_doc_number] => 20240184580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => Tracking of Data Readiness for Load and Store Operations [patent_app_type] => utility [patent_app_number] => 18/328839 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328839 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328839
Tracking of Data Readiness for Load and Store Operations Jun 4, 2023 Pending
Array ( [id] => 19617376 [patent_doc_number] => 20240403056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => SHADER LAUNCH SCHEDULING OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/205699 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205699 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/205699
SHADER LAUNCH SCHEDULING OPTIMIZATION Jun 4, 2023 Pending
Array ( [id] => 19514157 [patent_doc_number] => 20240345843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SYSTEMS AND METHODS FOR PROCESSING FORMATTED DATA IN COMPUTATIONAL STORAGE [patent_app_type] => utility [patent_app_number] => 18/328688 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8170 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328688 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328688
Systems and methods for processing formatted data in computational storage Jun 1, 2023 Issued
Array ( [id] => 19069436 [patent_doc_number] => 20240103862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => COMPUTING DEVICE AND COMPUTING METHOD [patent_app_type] => utility [patent_app_number] => 18/326202 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326202 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/326202
COMPUTING DEVICE AND COMPUTING METHOD May 30, 2023 Pending
Array ( [id] => 20215041 [patent_doc_number] => 12411694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Processor having adaptive pipeline with latency reduction logic that selectively executes instructions to reduce latency [patent_app_type] => utility [patent_app_number] => 18/314264 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314264 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314264
Processor having adaptive pipeline with latency reduction logic that selectively executes instructions to reduce latency May 8, 2023 Issued
Array ( [id] => 19917819 [patent_doc_number] => 12293189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Data value prediction and pre-alignment based on prefetched predicted memory access address [patent_app_type] => utility [patent_app_number] => 18/312059 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7006 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312059 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312059
Data value prediction and pre-alignment based on prefetched predicted memory access address May 3, 2023 Issued
Array ( [id] => 20374071 [patent_doc_number] => 12481505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Managing speculative instruction execution using speculative id in a graphflow apparatus [patent_app_type] => utility [patent_app_number] => 18/312365 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 12423 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312365 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312365
Managing speculative instruction execution using speculative id in a graphflow apparatus May 3, 2023 Issued
Array ( [id] => 19122753 [patent_doc_number] => 11966742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Apparatuses, methods, and systems for instructions to request a history reset of a processor core [patent_app_type] => utility [patent_app_number] => 18/311810 [patent_app_country] => US [patent_app_date] => 2023-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 28482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311810 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/311810
Apparatuses, methods, and systems for instructions to request a history reset of a processor core May 2, 2023 Issued
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