Search

Keith E. Vicary

Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
798
Issued Applications
429
Pending Applications
76
Abandoned Applications
310

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5467461 [patent_doc_number] => 20090327661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'MECHANISMS TO HANDLE FREE PHYSICAL REGISTER IDENTIFIERS FOR SMT OUT-OF-ORDER PROCESSORS' [patent_app_type] => utility [patent_app_number] => 12/165186 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20090327661.pdf [firstpage_image] =>[orig_patent_app_number] => 12165186 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165186
MECHANISMS TO HANDLE FREE PHYSICAL REGISTER IDENTIFIERS FOR SMT OUT-OF-ORDER PROCESSORS Jun 29, 2008 Abandoned
Array ( [id] => 5467857 [patent_doc_number] => 20090328057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'SYSTEM AND METHOD FOR RESERVATION STATION LOAD DEPENDENCY MATRIX' [patent_app_type] => utility [patent_app_number] => 12/164666 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6503 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0328/20090328057.pdf [firstpage_image] =>[orig_patent_app_number] => 12164666 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/164666
System and method for reservation station load dependency matrix Jun 29, 2008 Issued
Array ( [id] => 5467463 [patent_doc_number] => 20090327663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'Power Aware Retirement' [patent_app_type] => utility [patent_app_number] => 12/215526 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4619 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20090327663.pdf [firstpage_image] =>[orig_patent_app_number] => 12215526 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/215526
Selectively powered retirement unit using a partitioned allocation array and a partitioned writeback array Jun 26, 2008 Issued
Array ( [id] => 5351460 [patent_doc_number] => 20090006821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PROCESSING INFORMATION BY CONTROLLING ARITHMETIC MODE' [patent_app_type] => utility [patent_app_number] => 12/147897 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 16286 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006821.pdf [firstpage_image] =>[orig_patent_app_number] => 12147897 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/147897
Controlling arithmetic processing according to asynchronous and synchronous modes based upon data size threshold Jun 26, 2008 Issued
Array ( [id] => 5467474 [patent_doc_number] => 20090327674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'Loop Control System and Method' [patent_app_type] => utility [patent_app_number] => 12/147893 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7342 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20090327674.pdf [firstpage_image] =>[orig_patent_app_number] => 12147893 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/147893
Loop Control System and Method Jun 26, 2008 Abandoned
Array ( [id] => 5577119 [patent_doc_number] => 20090144481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'Enhanced Microprocessor or Microcontroller' [patent_app_type] => utility [patent_app_number] => 12/147746 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8381 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20090144481.pdf [firstpage_image] =>[orig_patent_app_number] => 12147746 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/147746
Context switching with automatic saving of special function registers memory-mapped to all banks Jun 26, 2008 Issued
Array ( [id] => 4761213 [patent_doc_number] => 20080313439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'PIPELINE DEVICE WITH A PLURALITY OF PIPELINED PROCESSING UNITS' [patent_app_type] => utility [patent_app_number] => 12/138723 [patent_app_country] => US [patent_app_date] => 2008-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 25303 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313439.pdf [firstpage_image] =>[orig_patent_app_number] => 12138723 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/138723
PIPELINE DEVICE WITH A PLURALITY OF PIPELINED PROCESSING UNITS Jun 12, 2008 Abandoned
Array ( [id] => 4589558 [patent_doc_number] => 07861070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Trace compression method for debug and trace interface wherein differences of register contents between logically adjacent registers are packed and increases of program counter addresses are categorized' [patent_app_type] => utility [patent_app_number] => 12/138226 [patent_app_country] => US [patent_app_date] => 2008-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2576 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/861/07861070.pdf [firstpage_image] =>[orig_patent_app_number] => 12138226 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/138226
Trace compression method for debug and trace interface wherein differences of register contents between logically adjacent registers are packed and increases of program counter addresses are categorized Jun 11, 2008 Issued
Array ( [id] => 5371683 [patent_doc_number] => 20090309243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'MULTI-CORE INTEGRATED CIRCUITS HAVING ASYMMETRIC PERFORMANCE BETWEEN CORES' [patent_app_type] => utility [patent_app_number] => 12/137053 [patent_app_country] => US [patent_app_date] => 2008-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20090309243.pdf [firstpage_image] =>[orig_patent_app_number] => 12137053 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/137053
MULTI-CORE INTEGRATED CIRCUITS HAVING ASYMMETRIC PERFORMANCE BETWEEN CORES Jun 10, 2008 Abandoned
Array ( [id] => 8220021 [patent_doc_number] => 08195896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Resource sharing techniques in a parallel processing computing system utilizing locks by replicating or shadowing execution contexts' [patent_app_type] => utility [patent_app_number] => 12/136166 [patent_app_country] => US [patent_app_date] => 2008-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 10794 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/195/08195896.pdf [firstpage_image] =>[orig_patent_app_number] => 12136166 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/136166
Resource sharing techniques in a parallel processing computing system utilizing locks by replicating or shadowing execution contexts Jun 9, 2008 Issued
Array ( [id] => 5369914 [patent_doc_number] => 20090307473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'METHOD FOR ADOPTING SEQUENTIAL PROCESSING FROM A PARALLEL PROCESSING ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 12/135890 [patent_app_country] => US [patent_app_date] => 2008-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7817 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20090307473.pdf [firstpage_image] =>[orig_patent_app_number] => 12135890 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/135890
Method for re-sequencing commands and data between a master and target devices utilizing parallel processing Jun 8, 2008 Issued
Array ( [id] => 4581475 [patent_doc_number] => 07840787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Method and apparatus for non-deterministic incremental program replay using checkpoints and syndrome tracking' [patent_app_type] => utility [patent_app_number] => 12/125370 [patent_app_country] => US [patent_app_date] => 2008-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840787.pdf [firstpage_image] =>[orig_patent_app_number] => 12125370 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/125370
Method and apparatus for non-deterministic incremental program replay using checkpoints and syndrome tracking May 21, 2008 Issued
Array ( [id] => 4678220 [patent_doc_number] => 20080215851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Method and arrangement for the power-efficient control of processors' [patent_app_type] => utility [patent_app_number] => 12/151202 [patent_app_country] => US [patent_app_date] => 2008-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2188 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20080215851.pdf [firstpage_image] =>[orig_patent_app_number] => 12151202 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/151202
Method and arrangement for the power-efficient control of processors May 4, 2008 Abandoned
Array ( [id] => 5475881 [patent_doc_number] => 20090249047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'METHOD AND SYSTEM FOR RELATIVE MULTIPLE-TARGET BRANCH INSTRUCTION EXECUTION IN A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/059957 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2103 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20090249047.pdf [firstpage_image] =>[orig_patent_app_number] => 12059957 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/059957
METHOD AND SYSTEM FOR RELATIVE MULTIPLE-TARGET BRANCH INSTRUCTION EXECUTION IN A PROCESSOR Mar 30, 2008 Abandoned
Array ( [id] => 5475882 [patent_doc_number] => 20090249048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'BRANCH TARGET BUFFER ADDRESSING IN A DATA PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/057543 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20090249048.pdf [firstpage_image] =>[orig_patent_app_number] => 12057543 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/057543
BRANCH TARGET BUFFER ADDRESSING IN A DATA PROCESSOR Mar 27, 2008 Abandoned
Array ( [id] => 4448946 [patent_doc_number] => 07865698 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-04 [patent_title] => 'Decode mode for an auxiliary processor unit controller in which an opcode is partially masked such that a configuration register defines a plurality of user defined instructions' [patent_app_type] => utility [patent_app_number] => 12/057356 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6180 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865698.pdf [firstpage_image] =>[orig_patent_app_number] => 12057356 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/057356
Decode mode for an auxiliary processor unit controller in which an opcode is partially masked such that a configuration register defines a plurality of user defined instructions Mar 26, 2008 Issued
Array ( [id] => 6646732 [patent_doc_number] => 20100174891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'RECONFIGURABLE SIMD PROCESSOR AND METHOD FOR CONTROLLING ITS INSTRUCTION EXECUTION' [patent_app_type] => utility [patent_app_number] => 12/593498 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 17602 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20100174891.pdf [firstpage_image] =>[orig_patent_app_number] => 12593498 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/593498
RECONFIGURABLE SIMD PROCESSOR AND METHOD FOR CONTROLLING ITS INSTRUCTION EXECUTION Mar 26, 2008 Abandoned
Array ( [id] => 38212 [patent_doc_number] => 07788470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-31 [patent_title] => 'Shadow pipeline in an auxiliary processor unit controller' [patent_app_type] => utility [patent_app_number] => 12/057353 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9058 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/788/07788470.pdf [firstpage_image] =>[orig_patent_app_number] => 12057353 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/057353
Shadow pipeline in an auxiliary processor unit controller Mar 26, 2008 Issued
Array ( [id] => 4761219 [patent_doc_number] => 20080313445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'METHOD AND SYSTEM FOR PREVENTING LIVELOCK DUE TO COMPETING UPDATES OF PREDICTION INFORMATION' [patent_app_type] => utility [patent_app_number] => 12/051322 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7444 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313445.pdf [firstpage_image] =>[orig_patent_app_number] => 12051322 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051322
Method and system for preventing livelock due to competing updates of prediction information Mar 18, 2008 Issued
Array ( [id] => 8220075 [patent_doc_number] => 08195925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Apparatus and method for efficient caching via addition of branch into program block being processed' [patent_app_type] => utility [patent_app_number] => 12/051260 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10929 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/195/08195925.pdf [firstpage_image] =>[orig_patent_app_number] => 12051260 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051260
Apparatus and method for efficient caching via addition of branch into program block being processed Mar 18, 2008 Issued
Menu