Search

Keith E. Vicary

Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
798
Issued Applications
429
Pending Applications
76
Abandoned Applications
310

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5381392 [patent_doc_number] => 20090193231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'METHOD AND APPARATUS FOR THREAD PRIORITY CONTROL IN A MULTI-THREADED PROCESSOR OF AN INFORMATION HANDLING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/023004 [patent_app_country] => US [patent_app_date] => 2008-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6014 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20090193231.pdf [firstpage_image] =>[orig_patent_app_number] => 12023004 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/023004
Method and apparatus for thread priority control in a multi-threaded processor based upon branch issue information including branch confidence information Jan 29, 2008 Issued
Array ( [id] => 5381395 [patent_doc_number] => 20090193234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'SEQUENCER CONTROLLED SYSTEM AND METHOD FOR CONTROLLING TIMING OF OPERATIONS OF FUNCTIONAL UNITS' [patent_app_type] => utility [patent_app_number] => 12/019965 [patent_app_country] => US [patent_app_date] => 2008-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3928 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20090193234.pdf [firstpage_image] =>[orig_patent_app_number] => 12019965 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/019965
Sequencer controlled system and method for controlling timing of operations of functional units Jan 24, 2008 Issued
Array ( [id] => 5356562 [patent_doc_number] => 20090187906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'SEMI-ORDERED TRANSACTIONS' [patent_app_type] => utility [patent_app_number] => 12/018417 [patent_app_country] => US [patent_app_date] => 2008-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6195 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20090187906.pdf [firstpage_image] =>[orig_patent_app_number] => 12018417 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/018417
SEMI-ORDERED TRANSACTIONS Jan 22, 2008 Abandoned
Array ( [id] => 5356404 [patent_doc_number] => 20090187748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'METHOD AND SYSTEM FOR DETECTING STACK ALTERATION' [patent_app_type] => utility [patent_app_number] => 12/017625 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2679 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20090187748.pdf [firstpage_image] =>[orig_patent_app_number] => 12017625 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/017625
METHOD AND SYSTEM FOR DETECTING STACK ALTERATION Jan 21, 2008 Abandoned
Array ( [id] => 5356403 [patent_doc_number] => 20090187747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'SYSTEM AND METHOD FOR TRACING INSTRUCTION POINTERS AND DATA ACCESS' [patent_app_type] => utility [patent_app_number] => 12/016347 [patent_app_country] => US [patent_app_date] => 2008-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3361 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20090187747.pdf [firstpage_image] =>[orig_patent_app_number] => 12016347 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/016347
SYSTEM AND METHOD FOR TRACING INSTRUCTION POINTERS AND DATA ACCESS Jan 17, 2008 Abandoned
Array ( [id] => 5437784 [patent_doc_number] => 20090172371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'FEEDBACK MECHANISM FOR DYNAMIC PREDICATION OF INDIRECT JUMPS' [patent_app_type] => utility [patent_app_number] => 11/967336 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172371.pdf [firstpage_image] =>[orig_patent_app_number] => 11967336 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967336
Feedback mechanism for dynamic predication of indirect jumps Dec 30, 2007 Issued
Array ( [id] => 5437771 [patent_doc_number] => 20090172358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'IN-LANE VECTOR SHUFFLE INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 11/967211 [patent_app_country] => US [patent_app_date] => 2007-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5220 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172358.pdf [firstpage_image] =>[orig_patent_app_number] => 11967211 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967211
Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits Dec 29, 2007 Issued
Array ( [id] => 10589474 [patent_doc_number] => 09311085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Compiler assisted low power and high performance load handling based on load types' [patent_app_type] => utility [patent_app_number] => 11/967230 [patent_app_country] => US [patent_app_date] => 2007-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6543 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11967230 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967230
Compiler assisted low power and high performance load handling based on load types Dec 29, 2007 Issued
Array ( [id] => 5437768 [patent_doc_number] => 20090172355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'INSTRUCTIONS WITH FLOATING POINT CONTROL OVERRIDE' [patent_app_type] => utility [patent_app_number] => 11/967145 [patent_app_country] => US [patent_app_date] => 2007-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4666 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172355.pdf [firstpage_image] =>[orig_patent_app_number] => 11967145 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967145
Instructions with floating point control override Dec 28, 2007 Issued
11/966990 Transferring And Storing Data In Multicore And Multiprocessor Architectures Dec 27, 2007 Abandoned
Array ( [id] => 7779880 [patent_doc_number] => 08122230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Using a processor identification instruction to provide multi-level processor topology information' [patent_app_type] => utility [patent_app_number] => 11/966924 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122230.pdf [firstpage_image] =>[orig_patent_app_number] => 11966924 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/966924
Using a processor identification instruction to provide multi-level processor topology information Dec 27, 2007 Issued
Array ( [id] => 4665439 [patent_doc_number] => 20080256346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'CENTRAL PROCESSING UNIT HAVING BRANCH INSTRUCTION VERIFICATION UNIT FOR SECURE PROGRAM EXECUTION' [patent_app_type] => utility [patent_app_number] => 11/965003 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9398 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20080256346.pdf [firstpage_image] =>[orig_patent_app_number] => 11965003 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/965003
Central processing unit having branch instruction verification unit for secure program execution Dec 26, 2007 Issued
Array ( [id] => 5437781 [patent_doc_number] => 20090172368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'Hardware Based Runtime Error Detection' [patent_app_type] => utility [patent_app_number] => 11/964684 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172368.pdf [firstpage_image] =>[orig_patent_app_number] => 11964684 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/964684
Hardware Based Runtime Error Detection Dec 25, 2007 Abandoned
Array ( [id] => 5437761 [patent_doc_number] => 20090172348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'METHODS, APPARATUS, AND INSTRUCTIONS FOR PROCESSING VECTOR DATA' [patent_app_type] => utility [patent_app_number] => 11/964604 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5124 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172348.pdf [firstpage_image] =>[orig_patent_app_number] => 11964604 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/964604
METHODS, APPARATUS, AND INSTRUCTIONS FOR PROCESSING VECTOR DATA Dec 25, 2007 Abandoned
Array ( [id] => 9348087 [patent_doc_number] => 08667250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Methods, apparatus, and instructions for converting vector data' [patent_app_type] => utility [patent_app_number] => 11/964631 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6529 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11964631 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/964631
Methods, apparatus, and instructions for converting vector data Dec 25, 2007 Issued
Array ( [id] => 5430254 [patent_doc_number] => 20090089564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Protecting a Branch Instruction from Side Channel Vulnerabilities' [patent_app_type] => utility [patent_app_number] => 11/951999 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20090089564.pdf [firstpage_image] =>[orig_patent_app_number] => 11951999 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/951999
Protecting a Branch Instruction from Side Channel Vulnerabilities Dec 5, 2007 Abandoned
Array ( [id] => 5424192 [patent_doc_number] => 20090150648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'Vector Permute and Vector Register File Write Mask Instruction Variant State Extension for RISC Length Vector Instructions' [patent_app_type] => utility [patent_app_number] => 11/951416 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20090150648.pdf [firstpage_image] =>[orig_patent_app_number] => 11951416 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/951416
Vector Permute and Vector Register File Write Mask Instruction Variant State Extension for RISC Length Vector Instructions Dec 5, 2007 Abandoned
Array ( [id] => 4787661 [patent_doc_number] => 20080140990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Accelerator, Information Processing Apparatus and Information Processing Method' [patent_app_type] => utility [patent_app_number] => 11/950901 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9618 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20080140990.pdf [firstpage_image] =>[orig_patent_app_number] => 11950901 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/950901
Accelerator load balancing with dynamic frequency and voltage reduction Dec 4, 2007 Issued
Array ( [id] => 4836633 [patent_doc_number] => 20080133899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Context switching method, medium, and system for reconfigurable processors' [patent_app_type] => utility [patent_app_number] => 11/987662 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4670 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20080133899.pdf [firstpage_image] =>[orig_patent_app_number] => 11987662 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/987662
Context switching method, medium, and system for reconfigurable processors Dec 2, 2007 Abandoned
Array ( [id] => 18872 [patent_doc_number] => 07809927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Computation parallelization in software reconfigurable all digital phase lock loop' [patent_app_type] => utility [patent_app_number] => 11/949310 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 42 [patent_no_of_words] => 17048 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/809/07809927.pdf [firstpage_image] =>[orig_patent_app_number] => 11949310 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/949310
Computation parallelization in software reconfigurable all digital phase lock loop Dec 2, 2007 Issued
Menu