Search

Keith E. Vicary

Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
798
Issued Applications
429
Pending Applications
76
Abandoned Applications
310

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4945468 [patent_doc_number] => 20080082795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Twice issued conditional move instruction, and applications thereof' [patent_app_type] => utility [patent_app_number] => 11/640491 [patent_app_country] => US [patent_app_date] => 2006-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4689 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20080082795.pdf [firstpage_image] =>[orig_patent_app_number] => 11640491 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/640491
Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated Dec 17, 2006 Issued
Array ( [id] => 4829947 [patent_doc_number] => 20080126747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'METHODS AND APPARATUS TO IMPLEMENT HIGH-PERFORMANCE COMPUTING' [patent_app_type] => utility [patent_app_number] => 11/564086 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4498 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20080126747.pdf [firstpage_image] =>[orig_patent_app_number] => 11564086 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/564086
METHODS AND APPARATUS TO IMPLEMENT HIGH-PERFORMANCE COMPUTING Nov 27, 2006 Abandoned
Array ( [id] => 8378238 [patent_doc_number] => 08261046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Access of register files of other threads using synchronization' [patent_app_type] => utility [patent_app_number] => 12/446930 [patent_app_country] => US [patent_app_date] => 2006-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5371 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12446930 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/446930
Access of register files of other threads using synchronization Oct 26, 2006 Issued
Array ( [id] => 4923534 [patent_doc_number] => 20080071851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Instruction and logic for performing a dot-product operation' [patent_app_type] => utility [patent_app_number] => 11/524852 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12172 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20080071851.pdf [firstpage_image] =>[orig_patent_app_number] => 11524852 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/524852
Instruction and logic for performing a dot-product operation Sep 19, 2006 Abandoned
Array ( [id] => 4793905 [patent_doc_number] => 20080294879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'Asynchronous Ripple Pipeline' [patent_app_type] => utility [patent_app_number] => 12/065636 [patent_app_country] => US [patent_app_date] => 2006-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6357 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20080294879.pdf [firstpage_image] =>[orig_patent_app_number] => 12065636 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/065636
Asynchronous ripple pipeline Sep 3, 2006 Issued
Array ( [id] => 5173564 [patent_doc_number] => 20070074003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method for reducing code size of program in code memory' [patent_app_type] => utility [patent_app_number] => 11/510730 [patent_app_country] => US [patent_app_date] => 2006-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7131 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20070074003.pdf [firstpage_image] =>[orig_patent_app_number] => 11510730 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/510730
Method for reducing code size of a program in code memory by dynamically storing an instruction into a memory location following a group of instructions indicated by an offset operand and either a length operand or a bitmask operand of an echo instruction Aug 27, 2006 Issued
Array ( [id] => 5150622 [patent_doc_number] => 20070050682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Processor and debugging device' [patent_app_type] => utility [patent_app_number] => 11/509797 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 11210 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20070050682.pdf [firstpage_image] =>[orig_patent_app_number] => 11509797 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/509797
Processor and debugging device Aug 24, 2006 Abandoned
Array ( [id] => 5601947 [patent_doc_number] => 20060292292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Digital communications processor' [patent_app_type] => utility [patent_app_number] => 11/510545 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 38255 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20060292292.pdf [firstpage_image] =>[orig_patent_app_number] => 11510545 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/510545
High speed and high throughput digital communications processor with efficient cooperation between programmable processing components Aug 24, 2006 Issued
Array ( [id] => 157805 [patent_doc_number] => 07685405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-23 [patent_title] => 'Programmable architecture for digital communication systems that support vector processing and the associated methodology' [patent_app_type] => utility [patent_app_number] => 11/510246 [patent_app_country] => US [patent_app_date] => 2006-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9505 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685405.pdf [firstpage_image] =>[orig_patent_app_number] => 11510246 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/510246
Programmable architecture for digital communication systems that support vector processing and the associated methodology Aug 23, 2006 Issued
Array ( [id] => 4671638 [patent_doc_number] => 20080046699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'Method and apparatus for non-deterministic incremental program replay using checkpoints and syndrome tracking' [patent_app_type] => utility [patent_app_number] => 11/507166 [patent_app_country] => US [patent_app_date] => 2006-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20080046699.pdf [firstpage_image] =>[orig_patent_app_number] => 11507166 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/507166
Method and apparatus for non-deterministic incremental program replay using checkpoints and syndrome tracking Aug 20, 2006 Abandoned
Array ( [id] => 4671628 [patent_doc_number] => 20080046689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'Method and apparatus for cooperative multithreading' [patent_app_type] => utility [patent_app_number] => 11/506805 [patent_app_country] => US [patent_app_date] => 2006-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4148 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20080046689.pdf [firstpage_image] =>[orig_patent_app_number] => 11506805 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/506805
Method and apparatus for cooperative multithreading Aug 20, 2006 Abandoned
Array ( [id] => 5001299 [patent_doc_number] => 20070043933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'INSTRUCTION SET ARCHITECTURE EMPLOYING CONDITIONAL MULTISTORE SYNCHRONIZATION' [patent_app_type] => utility [patent_app_number] => 11/465383 [patent_app_country] => US [patent_app_date] => 2006-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10043 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20070043933.pdf [firstpage_image] =>[orig_patent_app_number] => 11465383 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465383
Instruction set architecture employing conditional multistore synchronization Aug 16, 2006 Issued
Array ( [id] => 9102674 [patent_doc_number] => 08566568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Method and apparatus for executing processor instructions based on a dynamically alterable delay' [patent_app_type] => utility [patent_app_number] => 11/464839 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4347 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11464839 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/464839
Method and apparatus for executing processor instructions based on a dynamically alterable delay Aug 15, 2006 Issued
Array ( [id] => 146734 [patent_doc_number] => 07694108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Reconfigurable semiconductor device capable of controlling output timing of data' [patent_app_type] => utility [patent_app_number] => 11/504763 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 8944 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/694/07694108.pdf [firstpage_image] =>[orig_patent_app_number] => 11504763 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/504763
Reconfigurable semiconductor device capable of controlling output timing of data Aug 15, 2006 Issued
Array ( [id] => 4653334 [patent_doc_number] => 20080040591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'METHOD FOR DETERMINING BRANCH TARGET BUFFER (BTB) ALLOCATION FOR BRANCH INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 11/464112 [patent_app_country] => US [patent_app_date] => 2006-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8958 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040591.pdf [firstpage_image] =>[orig_patent_app_number] => 11464112 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/464112
METHOD FOR DETERMINING BRANCH TARGET BUFFER (BTB) ALLOCATION FOR BRANCH INSTRUCTIONS Aug 10, 2006 Abandoned
Array ( [id] => 4653333 [patent_doc_number] => 20080040590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'SELECTIVE BRANCH TARGET BUFFER (BTB) ALLOCAITON' [patent_app_type] => utility [patent_app_number] => 11/464108 [patent_app_country] => US [patent_app_date] => 2006-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040590.pdf [firstpage_image] =>[orig_patent_app_number] => 11464108 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/464108
SELECTIVE BRANCH TARGET BUFFER (BTB) ALLOCAITON Aug 10, 2006 Abandoned
Array ( [id] => 4829942 [patent_doc_number] => 20080126743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Reducing Stalls in a Processor Pipeline' [patent_app_type] => utility [patent_app_number] => 11/462469 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5781 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20080126743.pdf [firstpage_image] =>[orig_patent_app_number] => 11462469 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/462469
Reducing Stalls in a Processor Pipeline Aug 3, 2006 Abandoned
Array ( [id] => 4690006 [patent_doc_number] => 20080034187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Method and Apparatus for Prefetching Non-Sequential Instruction Addresses' [patent_app_type] => utility [patent_app_number] => 11/461883 [patent_app_country] => US [patent_app_date] => 2006-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7158 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20080034187.pdf [firstpage_image] =>[orig_patent_app_number] => 11461883 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461883
Method and apparatus for prefetching non-sequential instruction addresses Aug 1, 2006 Issued
Array ( [id] => 5102815 [patent_doc_number] => 20070186077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'System and Method for Executing Instructions Utilizing a Preferred Slot Alignment Mechanism' [patent_app_type] => utility [patent_app_number] => 11/461554 [patent_app_country] => US [patent_app_date] => 2006-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 59 [patent_no_of_words] => 17141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20070186077.pdf [firstpage_image] =>[orig_patent_app_number] => 11461554 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461554
System and Method for Executing Instructions Utilizing a Preferred Slot Alignment Mechanism Jul 31, 2006 Abandoned
Array ( [id] => 5086970 [patent_doc_number] => 20070277021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'INSTRUCTION FOLDING FOR A STACK-BASED MACHINE' [patent_app_type] => utility [patent_app_number] => 11/461340 [patent_app_country] => US [patent_app_date] => 2006-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 48178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20070277021.pdf [firstpage_image] =>[orig_patent_app_number] => 11461340 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461340
INSTRUCTION FOLDING FOR A STACK-BASED MACHINE Jul 30, 2006 Abandoned
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