Search

Keith E. Vicary

Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
798
Issued Applications
429
Pending Applications
76
Abandoned Applications
310

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5668896 [patent_doc_number] => 20060174246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Processor and information processing method' [patent_app_type] => utility [patent_app_number] => 11/338835 [patent_app_country] => US [patent_app_date] => 2006-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4301 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20060174246.pdf [firstpage_image] =>[orig_patent_app_number] => 11338835 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/338835
Processor and information processing method Jan 24, 2006 Abandoned
Array ( [id] => 116496 [patent_doc_number] => 07721074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Conditional branch execution in a processor having a read-tie instruction and a data mover engine that associates register addresses with memory addresses' [patent_app_type] => utility [patent_app_number] => 11/336937 [patent_app_country] => US [patent_app_date] => 2006-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 11276 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/721/07721074.pdf [firstpage_image] =>[orig_patent_app_number] => 11336937 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/336937
Conditional branch execution in a processor having a read-tie instruction and a data mover engine that associates register addresses with memory addresses Jan 22, 2006 Issued
Array ( [id] => 116495 [patent_doc_number] => 07721073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Conditional branch execution in a processor having a data mover engine that associates register addresses with memory addresses' [patent_app_type] => utility [patent_app_number] => 11/336923 [patent_app_country] => US [patent_app_date] => 2006-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 11246 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/721/07721073.pdf [firstpage_image] =>[orig_patent_app_number] => 11336923 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/336923
Conditional branch execution in a processor having a data mover engine that associates register addresses with memory addresses Jan 22, 2006 Issued
Array ( [id] => 116502 [patent_doc_number] => 07721075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses' [patent_app_type] => utility [patent_app_number] => 11/336938 [patent_app_country] => US [patent_app_date] => 2006-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 11247 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/721/07721075.pdf [firstpage_image] =>[orig_patent_app_number] => 11336938 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/336938
Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses Jan 22, 2006 Issued
Array ( [id] => 8985096 [patent_doc_number] => 08516226 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-20 [patent_title] => 'Executing a prefetching policy responsive to entry into an execution phase of an application' [patent_app_type] => utility [patent_app_number] => 11/337425 [patent_app_country] => US [patent_app_date] => 2006-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3303 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11337425 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/337425
Executing a prefetching policy responsive to entry into an execution phase of an application Jan 22, 2006 Issued
Array ( [id] => 4990689 [patent_doc_number] => 20070157030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Cryptographic system component' [patent_app_type] => utility [patent_app_number] => 11/323329 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9158 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20070157030.pdf [firstpage_image] =>[orig_patent_app_number] => 11323329 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/323329
Cryptographic system component Dec 29, 2005 Abandoned
Array ( [id] => 5121867 [patent_doc_number] => 20070143582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'System and method for grouping execution threads' [patent_app_type] => utility [patent_app_number] => 11/305558 [patent_app_country] => US [patent_app_date] => 2005-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20070143582.pdf [firstpage_image] =>[orig_patent_app_number] => 11305558 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/305558
System and method for grouping execution threads Dec 15, 2005 Abandoned
Array ( [id] => 4862182 [patent_doc_number] => 20080270763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Device and Method for Processing Instructions' [patent_app_type] => utility [patent_app_number] => 12/097598 [patent_app_country] => US [patent_app_date] => 2005-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6292 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270763.pdf [firstpage_image] =>[orig_patent_app_number] => 12097598 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/097598
Device and method for processing instructions based on masked register group size information Dec 15, 2005 Issued
Array ( [id] => 4589515 [patent_doc_number] => 07861060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-28 [patent_title] => 'Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior' [patent_app_type] => utility [patent_app_number] => 11/305178 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 19083 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/861/07861060.pdf [firstpage_image] =>[orig_patent_app_number] => 11305178 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/305178
Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior Dec 14, 2005 Issued
Array ( [id] => 7598111 [patent_doc_number] => 07584342 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-01 [patent_title] => 'Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue' [patent_app_type] => utility [patent_app_number] => 11/305479 [patent_app_country] => US [patent_app_date] => 2005-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 18928 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/584/07584342.pdf [firstpage_image] =>[orig_patent_app_number] => 11305479 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/305479
Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue Dec 14, 2005 Issued
Array ( [id] => 5137480 [patent_doc_number] => 20070079109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Simulation apparatus and simulation method' [patent_app_type] => utility [patent_app_number] => 11/299894 [patent_app_country] => US [patent_app_date] => 2005-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3267 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20070079109.pdf [firstpage_image] =>[orig_patent_app_number] => 11299894 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/299894
Simulation apparatus and simulation method Dec 12, 2005 Abandoned
Array ( [id] => 9314906 [patent_doc_number] => 08656141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-18 [patent_title] => 'Architecture and programming in a parallel processing environment with switch-interconnected processors' [patent_app_type] => utility [patent_app_number] => 11/302956 [patent_app_country] => US [patent_app_date] => 2005-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 15738 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11302956 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/302956
Architecture and programming in a parallel processing environment with switch-interconnected processors Dec 12, 2005 Issued
Array ( [id] => 279910 [patent_doc_number] => 07558946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Breaking a lock situation in a processor without detection of the lock situation using a multi-level approach' [patent_app_type] => utility [patent_app_number] => 11/301058 [patent_app_country] => US [patent_app_date] => 2005-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5812 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558946.pdf [firstpage_image] =>[orig_patent_app_number] => 11301058 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/301058
Breaking a lock situation in a processor without detection of the lock situation using a multi-level approach Dec 11, 2005 Issued
Array ( [id] => 5852888 [patent_doc_number] => 20060236079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Unified single-core and multi-mode processor and its program execution method' [patent_app_type] => utility [patent_app_number] => 11/297395 [patent_app_country] => US [patent_app_date] => 2005-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2780 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20060236079.pdf [firstpage_image] =>[orig_patent_app_number] => 11297395 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/297395
Unified single-core and multi-mode processor and its program execution method Dec 8, 2005 Abandoned
Array ( [id] => 146493 [patent_doc_number] => 07689782 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-30 [patent_title] => 'Processor instruction used to determine whether to perform a memory-related trap' [patent_app_type] => utility [patent_app_number] => 11/296195 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4553 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/689/07689782.pdf [firstpage_image] =>[orig_patent_app_number] => 11296195 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/296195
Processor instruction used to determine whether to perform a memory-related trap Dec 5, 2005 Issued
Array ( [id] => 7687817 [patent_doc_number] => 20070106881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Bit-wise operation followed by byte-wise permutation for implementing DSP data manipulation instructions' [patent_app_type] => utility [patent_app_number] => 11/270213 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 5849 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20070106881.pdf [firstpage_image] =>[orig_patent_app_number] => 11270213 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/270213
Bit-wise operation followed by byte-wise permutation for implementing DSP data manipulation instructions Nov 7, 2005 Abandoned
Array ( [id] => 7687816 [patent_doc_number] => 20070106882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Byte-wise permutation facility configurable for implementing DSP data manipulation instructions' [patent_app_type] => utility [patent_app_number] => 11/270357 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 5999 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20070106882.pdf [firstpage_image] =>[orig_patent_app_number] => 11270357 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/270357
Byte-wise permutation facility configurable for implementing DSP data manipulation instructions Nov 7, 2005 Abandoned
Array ( [id] => 9023442 [patent_doc_number] => 08533439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Elastic shared RAM array including contiguous instruction and data portions distinct from each other' [patent_app_type] => utility [patent_app_number] => 11/268008 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4938 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11268008 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/268008
Elastic shared RAM array including contiguous instruction and data portions distinct from each other Nov 6, 2005 Issued
Array ( [id] => 7687815 [patent_doc_number] => 20070106883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Efficient Streaming of Un-Aligned Load/Store Instructions that Save Unused Non-Aligned Data in a Scratch Register for the Next Instruction' [patent_app_type] => utility [patent_app_number] => 11/164011 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6247 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20070106883.pdf [firstpage_image] =>[orig_patent_app_number] => 11164011 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/164011
Efficient Streaming of Un-Aligned Load/Store Instructions that Save Unused Non-Aligned Data in a Scratch Register for the Next Instruction Nov 6, 2005 Abandoned
Array ( [id] => 9472343 [patent_doc_number] => 08725990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-13 [patent_title] => 'Configurable SIMD engine with high, low and mixed precision modes' [patent_app_type] => utility [patent_app_number] => 11/267393 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8091 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11267393 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267393
Configurable SIMD engine with high, low and mixed precision modes Nov 3, 2005 Issued
Menu