Search

Keith E. Vicary

Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
798
Issued Applications
429
Pending Applications
76
Abandoned Applications
310

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4984376 [patent_doc_number] => 20070088935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Method and apparatus for delaying a load miss flush until issuing the dependent instruction' [patent_app_type] => utility [patent_app_number] => 11/252410 [patent_app_country] => US [patent_app_date] => 2005-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7258 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20070088935.pdf [firstpage_image] =>[orig_patent_app_number] => 11252410 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/252410
Method and apparatus for delaying a load miss flush until issuing the dependent instruction Oct 17, 2005 Issued
Array ( [id] => 4984380 [patent_doc_number] => 20070088939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Automatic and dynamic loading of instruction set architecture extensions' [patent_app_type] => utility [patent_app_number] => 11/252393 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20070088939.pdf [firstpage_image] =>[orig_patent_app_number] => 11252393 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/252393
Automatic and dynamic loading of instruction set architecture extensions Oct 16, 2005 Abandoned
Array ( [id] => 362556 [patent_doc_number] => 07487335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-03 [patent_title] => 'Method and apparatus for accessing registers during deferred execution' [patent_app_type] => utility [patent_app_number] => 11/251427 [patent_app_country] => US [patent_app_date] => 2005-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5038 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/487/07487335.pdf [firstpage_image] =>[orig_patent_app_number] => 11251427 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/251427
Method and apparatus for accessing registers during deferred execution Oct 13, 2005 Issued
Array ( [id] => 5755505 [patent_doc_number] => 20060224654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Method and system for performing digital signal processing operations in a computer system' [patent_app_type] => utility [patent_app_number] => 11/217651 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1924 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20060224654.pdf [firstpage_image] =>[orig_patent_app_number] => 11217651 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/217651
Method and system for performing digital signal processing operations in a computer system Aug 24, 2005 Abandoned
Array ( [id] => 5809539 [patent_doc_number] => 20060095895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Method and apparatus for inserting code' [patent_app_type] => utility [patent_app_number] => 11/212554 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5881 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095895.pdf [firstpage_image] =>[orig_patent_app_number] => 11212554 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212554
Method and apparatus for inserting code Aug 24, 2005 Abandoned
Array ( [id] => 5755504 [patent_doc_number] => 20060224653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Method and system for dynamic session control of digital signal processing operations' [patent_app_type] => utility [patent_app_number] => 11/212949 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2299 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20060224653.pdf [firstpage_image] =>[orig_patent_app_number] => 11212949 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212949
Method and system for dynamic session control of digital signal processing operations Aug 24, 2005 Abandoned
Array ( [id] => 5150541 [patent_doc_number] => 20070050601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Avoiding live-lock in a processor that supports speculative execution' [patent_app_type] => utility [patent_app_number] => 11/210557 [patent_app_country] => US [patent_app_date] => 2005-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4503 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20070050601.pdf [firstpage_image] =>[orig_patent_app_number] => 11210557 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/210557
Avoiding live-lock in a processor that supports speculative execution Aug 22, 2005 Issued
Array ( [id] => 5001300 [patent_doc_number] => 20070043934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Early misprediction recovery through periodic checkpoints' [patent_app_type] => utility [patent_app_number] => 11/208924 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4980 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20070043934.pdf [firstpage_image] =>[orig_patent_app_number] => 11208924 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/208924
Early misprediction recovery through periodic checkpoints Aug 21, 2005 Abandoned
Array ( [id] => 5809369 [patent_doc_number] => 20060095725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Method and apparatus for executing instructions from an auxiliary data stream' [patent_app_type] => utility [patent_app_number] => 11/203479 [patent_app_country] => US [patent_app_date] => 2005-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3667 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095725.pdf [firstpage_image] =>[orig_patent_app_number] => 11203479 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/203479
Method and apparatus for executing instructions from an auxiliary data stream Aug 11, 2005 Abandoned
Array ( [id] => 8001151 [patent_doc_number] => 08082423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates' [patent_app_type] => utility [patent_app_number] => 11/201683 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6529 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 526 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082423.pdf [firstpage_image] =>[orig_patent_app_number] => 11201683 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201683
Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates Aug 10, 2005 Issued
Array ( [id] => 5803770 [patent_doc_number] => 20060037010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Processor arrangement and method for operation thereof' [patent_app_type] => utility [patent_app_number] => 11/201655 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2523 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20060037010.pdf [firstpage_image] =>[orig_patent_app_number] => 11201655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201655
Processor arrangement and method for operation thereof Aug 10, 2005 Abandoned
Array ( [id] => 5114899 [patent_doc_number] => 20070198815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Programmable digital signal processor having a clustered SIMD microarchitecture including a complex short multiplier and an independent vector load unit' [patent_app_type] => utility [patent_app_number] => 11/201841 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7869 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20070198815.pdf [firstpage_image] =>[orig_patent_app_number] => 11201841 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201841
Programmable digital signal processor having a clustered SIMD microarchitecture including a complex short multiplier and an independent vector load unit Aug 10, 2005 Abandoned
Array ( [id] => 7595778 [patent_doc_number] => 07620804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Central processing unit architecture with multiple pipelines which decodes but does not execute both branch paths' [patent_app_type] => utility [patent_app_number] => 11/200020 [patent_app_country] => US [patent_app_date] => 2005-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2757 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/620/07620804.pdf [firstpage_image] =>[orig_patent_app_number] => 11200020 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/200020
Central processing unit architecture with multiple pipelines which decodes but does not execute both branch paths Aug 9, 2005 Issued
Array ( [id] => 7601949 [patent_doc_number] => 07237095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-26 [patent_title] => 'Optimum power efficient shifting algorithm for schedulers' [patent_app_type] => utility [patent_app_number] => 11/197705 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8727 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/237/07237095.pdf [firstpage_image] =>[orig_patent_app_number] => 11197705 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/197705
Optimum power efficient shifting algorithm for schedulers Aug 3, 2005 Issued
Array ( [id] => 5673926 [patent_doc_number] => 20060179281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Multithreading instruction scheduler employing thread group priorities' [patent_app_type] => utility [patent_app_number] => 11/191258 [patent_app_country] => US [patent_app_date] => 2005-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 40578 [patent_no_of_claims] => 87 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20060179281.pdf [firstpage_image] =>[orig_patent_app_number] => 11191258 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/191258
Multithreading instruction scheduler employing thread group priorities Jul 26, 2005 Issued
Array ( [id] => 5822258 [patent_doc_number] => 20060026571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Method and system of control flow graph construction' [patent_app_type] => utility [patent_app_number] => 11/189367 [patent_app_country] => US [patent_app_date] => 2005-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5939 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026571.pdf [firstpage_image] =>[orig_patent_app_number] => 11189367 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/189367
Method and system of control flow graph construction Jul 25, 2005 Issued
Array ( [id] => 5822090 [patent_doc_number] => 20060026403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Compare instruction' [patent_app_type] => utility [patent_app_number] => 11/188592 [patent_app_country] => US [patent_app_date] => 2005-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6653 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026403.pdf [firstpage_image] =>[orig_patent_app_number] => 11188592 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/188592
Modifying an instruction stream using one or more bits to replace an instruction or to replace an instruction and to subsequently execute the replaced instruction Jul 24, 2005 Issued
Array ( [id] => 5822088 [patent_doc_number] => 20060026401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Method and system to disable the \"wide\" prefix' [patent_app_type] => utility [patent_app_number] => 11/188336 [patent_app_country] => US [patent_app_date] => 2005-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4568 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026401.pdf [firstpage_image] =>[orig_patent_app_number] => 11188336 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/188336
Method and system to disable the "wide" prefix Jul 24, 2005 Abandoned
Array ( [id] => 5896458 [patent_doc_number] => 20060004997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Method and apparatus for computing' [patent_app_type] => utility [patent_app_number] => 11/183649 [patent_app_country] => US [patent_app_date] => 2005-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 71 [patent_figures_cnt] => 71 [patent_no_of_words] => 24996 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20060004997.pdf [firstpage_image] =>[orig_patent_app_number] => 11183649 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/183649
Method and apparatus for directing a computational array to execute a plurality of successive computational array instructions at runtime Jul 17, 2005 Issued
Array ( [id] => 890558 [patent_doc_number] => 07353369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-01 [patent_title] => 'System and method for managing divergent threads in a SIMD architecture' [patent_app_type] => utility [patent_app_number] => 11/180388 [patent_app_country] => US [patent_app_date] => 2005-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9328 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/353/07353369.pdf [firstpage_image] =>[orig_patent_app_number] => 11180388 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/180388
System and method for managing divergent threads in a SIMD architecture Jul 12, 2005 Issued
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