
Keith E. Vicary
Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2182, 2183 |
| Total Applications | 798 |
| Issued Applications | 429 |
| Pending Applications | 76 |
| Abandoned Applications | 310 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 28242
[patent_doc_number] => 07797520
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-14
[patent_title] => 'Early branch instruction prediction'
[patent_app_type] => utility
[patent_app_number] => 11/170083
[patent_app_country] => US
[patent_app_date] => 2005-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5014
[patent_no_of_claims] => 12
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[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/797/07797520.pdf
[firstpage_image] =>[orig_patent_app_number] => 11170083
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/170083 | Early branch instruction prediction | Jun 29, 2005 | Issued |
Array
(
[id] => 5243779
[patent_doc_number] => 20070022274
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Apparatus, system, and method of predicting and correcting critical paths'
[patent_app_type] => utility
[patent_app_number] => 11/168491
[patent_app_country] => US
[patent_app_date] => 2005-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4602
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20070022274.pdf
[firstpage_image] =>[orig_patent_app_number] => 11168491
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/168491 | Apparatus, system, and method of predicting and correcting critical paths | Jun 28, 2005 | Abandoned |
Array
(
[id] => 6932554
[patent_doc_number] => 20050283589
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-22
[patent_title] => 'Data processor'
[patent_app_type] => utility
[patent_app_number] => 11/152723
[patent_app_country] => US
[patent_app_date] => 2005-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
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[patent_no_of_words] => 42953
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[pdf_file] => publications/A1/0283/20050283589.pdf
[firstpage_image] =>[orig_patent_app_number] => 11152723
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/152723 | Data processor | Jun 14, 2005 | Abandoned |
Array
(
[id] => 5644366
[patent_doc_number] => 20060282821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-14
[patent_title] => 'Efficient subprogram return in microprocessors'
[patent_app_type] => utility
[patent_app_number] => 11/149611
[patent_app_country] => US
[patent_app_date] => 2005-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3275
[patent_no_of_claims] => 27
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[pdf_file] => publications/A1/0282/20060282821.pdf
[firstpage_image] =>[orig_patent_app_number] => 11149611
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/149611 | Efficient subprogram return in microprocessors | Jun 9, 2005 | Abandoned |
Array
(
[id] => 7057335
[patent_doc_number] => 20050278510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-15
[patent_title] => 'Pseudo register file write ports'
[patent_app_type] => utility
[patent_app_number] => 11/127779
[patent_app_country] => US
[patent_app_date] => 2005-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 8254
[patent_no_of_claims] => 23
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0278/20050278510.pdf
[firstpage_image] =>[orig_patent_app_number] => 11127779
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/127779 | Pseudo register file write ports | May 11, 2005 | Abandoned |
Array
(
[id] => 118174
[patent_doc_number] => 07716459
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-11
[patent_title] => 'Protection of a program jump from fault injection by masking a memory address with a random number'
[patent_app_type] => utility
[patent_app_number] => 11/126937
[patent_app_country] => US
[patent_app_date] => 2005-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2794
[patent_no_of_claims] => 29
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/716/07716459.pdf
[firstpage_image] =>[orig_patent_app_number] => 11126937
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/126937 | Protection of a program jump from fault injection by masking a memory address with a random number | May 10, 2005 | Issued |
Array
(
[id] => 5734620
[patent_doc_number] => 20060259737
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'Vector processor with special purpose registers and high speed memory access'
[patent_app_type] => utility
[patent_app_number] => 11/126522
[patent_app_country] => US
[patent_app_date] => 2005-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
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[patent_no_of_words] => 11386
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0259/20060259737.pdf
[firstpage_image] =>[orig_patent_app_number] => 11126522
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/126522 | Vector processor with special purpose registers and high speed memory access | May 9, 2005 | Abandoned |
Array
(
[id] => 7047056
[patent_doc_number] => 20050251651
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-10
[patent_title] => 'Microcomputer and dividing circuit'
[patent_app_type] => utility
[patent_app_number] => 11/120105
[patent_app_country] => US
[patent_app_date] => 2005-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 88
[patent_figures_cnt] => 88
[patent_no_of_words] => 39223
[patent_no_of_claims] => 2
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0251/20050251651.pdf
[firstpage_image] =>[orig_patent_app_number] => 11120105
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/120105 | Microcomputer and dividing circuit | May 2, 2005 | Abandoned |
Array
(
[id] => 5861639
[patent_doc_number] => 20060230253
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-12
[patent_title] => 'Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment'
[patent_app_type] => utility
[patent_app_number] => 11/103744
[patent_app_country] => US
[patent_app_date] => 2005-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 7685
[patent_no_of_claims] => 40
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[pdf_file] => publications/A1/0230/20060230253.pdf
[firstpage_image] =>[orig_patent_app_number] => 11103744
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/103744 | Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment | Apr 10, 2005 | Abandoned |
Array
(
[id] => 366606
[patent_doc_number] => 07484080
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-27
[patent_title] => 'Entering scout-mode when stores encountered during execute-ahead mode exceed the capacity of the store buffer'
[patent_app_type] => utility
[patent_app_number] => 11/103912
[patent_app_country] => US
[patent_app_date] => 2005-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 4816
[patent_no_of_claims] => 19
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[pdf_file] => patents/07/484/07484080.pdf
[firstpage_image] =>[orig_patent_app_number] => 11103912
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/103912 | Entering scout-mode when stores encountered during execute-ahead mode exceed the capacity of the store buffer | Apr 10, 2005 | Issued |
Array
(
[id] => 37534
[patent_doc_number] => 07793078
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-07
[patent_title] => 'Multiple instruction set data processing system with conditional branch instructions of a first instruction set and a second instruction set sharing a same instruction encoding'
[patent_app_type] => utility
[patent_app_number] => 11/095655
[patent_app_country] => US
[patent_app_date] => 2005-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2806
[patent_no_of_claims] => 22
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[pdf_file] => patents/07/793/07793078.pdf
[firstpage_image] =>[orig_patent_app_number] => 11095655
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/095655 | Multiple instruction set data processing system with conditional branch instructions of a first instruction set and a second instruction set sharing a same instruction encoding | Mar 31, 2005 | Issued |
Array
(
[id] => 5755722
[patent_doc_number] => 20060224871
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-05
[patent_title] => 'Wide branch target buffer'
[patent_app_type] => utility
[patent_app_number] => 11/095862
[patent_app_country] => US
[patent_app_date] => 2005-03-31
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11095862
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/095862 | Wide branch target buffer | Mar 30, 2005 | Abandoned |
Array
(
[id] => 5755718
[patent_doc_number] => 20060224867
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-05
[patent_title] => 'Avoiding unnecessary processing of predicated instructions'
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[firstpage_image] =>[orig_patent_app_number] => 11095681
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/095681 | Avoiding unnecessary processing of predicated instructions | Mar 30, 2005 | Abandoned |
Array
(
[id] => 5755715
[patent_doc_number] => 20060224864
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[patent_kind] => A1
[patent_issue_date] => 2006-10-05
[patent_title] => 'System and method for handling multi-cycle non-pipelined instruction sequencing'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/097741 | System and method for handling multi-cycle non-pipelined instruction sequencing | Mar 30, 2005 | Abandoned |
Array
(
[id] => 7021582
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[patent_title] => 'Data processing apparatus adopting pipeline processing system and data processing method used in the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/092705 | Data processing apparatus adopting pipeline processing system and data processing method used in the same | Mar 29, 2005 | Abandoned |
Array
(
[id] => 7021576
[patent_doc_number] => 20050223201
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[patent_issue_date] => 2005-10-06
[patent_title] => 'Facilitating rapid progress while speculatively executing code in scout mode'
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[patent_app_number] => 11/095644
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[firstpage_image] =>[orig_patent_app_number] => 11095644
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/095644 | Facilitating rapid progress while speculatively executing code in scout mode | Mar 29, 2005 | Abandoned |
Array
(
[id] => 171869
[patent_doc_number] => 07669037
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[patent_kind] => B1
[patent_issue_date] => 2010-02-23
[patent_title] => 'Method and apparatus for communication between a processor and hardware blocks in a programmable logic device'
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[patent_app_number] => 11/076797
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Array
(
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[patent_title] => 'Lookahead mode sequencer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/055862 | Method, apparatus and program product for enhancing performance of an in-order processor with long stalls | Feb 10, 2005 | Issued |
Array
(
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[patent_title] => 'Mini-refresh processor recovery as bug workaround method using existing recovery hardware'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/055823 | Mini-refresh processor recovery as bug workaround method using existing recovery hardware | Feb 10, 2005 | Abandoned |
Array
(
[id] => 7595781
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[patent_issue_date] => 2009-11-17
[patent_title] => 'Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor'
[patent_app_type] => utility
[patent_app_number] => 11/055848
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/055848 | Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor | Feb 10, 2005 | Issued |