Search

Keith E. Vicary

Examiner (ID: 15210)

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
804
Issued Applications
430
Pending Applications
77
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18772773 [patent_doc_number] => 20230367599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => Vector Gather with a Narrow Datapath [patent_app_type] => utility [patent_app_number] => 18/141466 [patent_app_country] => US [patent_app_date] => 2023-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141466 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141466
Vector Gather with a Narrow Datapath Apr 29, 2023 Pending
Array ( [id] => 18741705 [patent_doc_number] => 20230350686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => LOGIC CIRCUIT AND METHOD FOR CHECKING AND UPDATING PROGRAM COUNTER VALUES IN PIPELINE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/139914 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139914 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/139914
Logic circuit and method for checking and updating program counter values in pipeline architecture by comparing PC values of consecutive cycles Apr 25, 2023 Issued
Array ( [id] => 18727863 [patent_doc_number] => 20230342156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => APPARATUSES AND METHODS FOR SPECULATIVE EXECUTION SIDE CHANNEL MITIGATION [patent_app_type] => utility [patent_app_number] => 18/138591 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138591 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/138591
Apparatuses and methods for speculative execution side channel mitigation Apr 23, 2023 Issued
Array ( [id] => 19481951 [patent_doc_number] => 20240329993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => INSTRUCTIONS FOR WRITE AND/OR READ OF CONTROL AND/OR STATUS REGISTERS [patent_app_type] => utility [patent_app_number] => 18/193232 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18193232 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/193232
INSTRUCTIONS FOR WRITE AND/OR READ OF CONTROL AND/OR STATUS REGISTERS Mar 29, 2023 Pending
Array ( [id] => 19466328 [patent_doc_number] => 20240319998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => ON-CHIP AI COMPUTE HARDWARE ACCELERATION [patent_app_type] => utility [patent_app_number] => 18/187465 [patent_app_country] => US [patent_app_date] => 2023-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18187465 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/187465
ON-CHIP AI COMPUTE HARDWARE ACCELERATION Mar 20, 2023 Pending
Array ( [id] => 19725784 [patent_doc_number] => 20250028535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => DECODING METHOD, PROCESSOR, CHIP, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/714604 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18714604 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/714604
DECODING METHOD, PROCESSOR, CHIP, AND ELECTRONIC DEVICE Feb 26, 2023 Pending
Array ( [id] => 18614278 [patent_doc_number] => 20230281015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => Processing Device for Intermediate Value Scaling [patent_app_type] => utility [patent_app_number] => 18/175050 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18175050 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/175050
Processing device for intermediate value scaling Feb 26, 2023 Issued
Array ( [id] => 19405619 [patent_doc_number] => 20240289130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => DATA PROCESSING APPARATUS WITH SELECTIVELY DELAYED TRANSMISSION OF OPERANDS [patent_app_type] => utility [patent_app_number] => 18/174207 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174207 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/174207
Data processing apparatus with selectively delayed transmission of operands Feb 23, 2023 Issued
Array ( [id] => 19391383 [patent_doc_number] => 20240281253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => COMPRESSING INSTRUCTIONS FOR MACHINE-LEARNING ACCELERATORS [patent_app_type] => utility [patent_app_number] => 18/172016 [patent_app_country] => US [patent_app_date] => 2023-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18172016 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/172016
Compressing instructions for machine-learning accelerators Feb 20, 2023 Issued
Array ( [id] => 18677816 [patent_doc_number] => 20230315463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => METHODS AND DEVICES FOR DEFEATING BUFFER OVERFLOW PROBLEMS IN MULTI-CORE PROCESSORS [patent_app_type] => utility [patent_app_number] => 18/164122 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164122 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/164122
METHODS AND DEVICES FOR DEFEATING BUFFER OVERFLOW PROBLEMS IN MULTI-CORE PROCESSORS Feb 2, 2023 Pending
Array ( [id] => 18407544 [patent_doc_number] => 20230168897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection Network [patent_app_type] => utility [patent_app_number] => 18/101715 [patent_app_country] => US [patent_app_date] => 2023-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 60798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18101715 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/101715
System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network Jan 25, 2023 Issued
Array ( [id] => 19320148 [patent_doc_number] => 20240241692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => Sorting Method and Control for Partially Ordered Data Arrays in Embedded Systems [patent_app_type] => utility [patent_app_number] => 18/096115 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4368 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096115 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096115
Sorting Method and Control for Partially Ordered Data Arrays in Embedded Systems Jan 11, 2023 Pending
Array ( [id] => 19267550 [patent_doc_number] => 20240211253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => ACCELERATING KECCAK ALGORITHMS [patent_app_type] => utility [patent_app_number] => 18/145744 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18145744 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/145744
ACCELERATING KECCAK ALGORITHMS Dec 21, 2022 Pending
Array ( [id] => 18336580 [patent_doc_number] => 20230128529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => ACCELERATION SYSTEM, METHOD AND STORAGE MEDIUM BASED ON CONVOLUTIONAL NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 18/145028 [patent_app_country] => US [patent_app_date] => 2022-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18145028 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/145028
ACCELERATION SYSTEM, METHOD AND STORAGE MEDIUM BASED ON CONVOLUTIONAL NEURAL NETWORK Dec 21, 2022 Abandoned
Array ( [id] => 19669816 [patent_doc_number] => 12182575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Performance monitoring information informed register renaming [patent_app_type] => utility [patent_app_number] => 18/079308 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 14866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18079308 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/079308
Performance monitoring information informed register renaming Dec 11, 2022 Issued
Array ( [id] => 19235762 [patent_doc_number] => 20240192957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => BRANCH TARGET BUFFER ACCESS SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/064157 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064157 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/064157
BRANCH TARGET BUFFER ACCESS SYSTEMS AND METHODS Dec 8, 2022 Pending
Array ( [id] => 19053062 [patent_doc_number] => 20240095031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => Thread Channel Deactivation based on Instruction Cache Misses [patent_app_type] => utility [patent_app_number] => 18/054380 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18054380 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/054380
Thread channel deactivation based on instruction cache misses Nov 9, 2022 Issued
Array ( [id] => 18182653 [patent_doc_number] => 20230043383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => SYSTEMS AND METHODS FOR VIRTUALLY PARTITIONING A MACHINE PERCEPTION AND DENSE ALGORITHM INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/967862 [patent_app_country] => US [patent_app_date] => 2022-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17967862 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/967862
Systems and methods for virtually partitioning a machine perception and dense algorithm integrated circuit Oct 16, 2022 Issued
Array ( [id] => 18839382 [patent_doc_number] => 11847456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Livelock recovery circuit for detecting illegal repetition of an instruction and transitioning to a known state [patent_app_type] => utility [patent_app_number] => 17/961497 [patent_app_country] => US [patent_app_date] => 2022-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 13160 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961497 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/961497
Livelock recovery circuit for detecting illegal repetition of an instruction and transitioning to a known state Oct 5, 2022 Issued
Array ( [id] => 19243738 [patent_doc_number] => 12014183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Base plus offset addressing for load/store messages [patent_app_type] => utility [patent_app_number] => 17/949904 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 57 [patent_no_of_words] => 49539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949904 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/949904
Base plus offset addressing for load/store messages Sep 20, 2022 Issued
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