Search

Keith E. Vicary

Examiner (ID: 11479, Phone: (571)270-1314 , Office: P/2182 )

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
798
Issued Applications
429
Pending Applications
76
Abandoned Applications
310

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5615238 [patent_doc_number] => 20060117167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Processing activity masking in a data processing system' [patent_app_type] => utility [patent_app_number] => 10/527812 [patent_app_country] => US [patent_app_date] => 2003-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5906 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20060117167.pdf [firstpage_image] =>[orig_patent_app_number] => 10527812 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/527812
Processing activity masking in a data processing system Oct 5, 2003 Abandoned
Array ( [id] => 7118858 [patent_doc_number] => 20050071605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'METHOD FOR ENABLING A BRANCH-CONTROL SYSTEM IN A MICROCOMPUTER APPARATUS' [patent_app_type] => utility [patent_app_number] => 10/605418 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4020 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20050071605.pdf [firstpage_image] =>[orig_patent_app_number] => 10605418 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/605418
METHOD FOR ENABLING A BRANCH-CONTROL SYSTEM IN A MICROCOMPUTER APPARATUS Sep 29, 2003 Abandoned
Array ( [id] => 7118612 [patent_doc_number] => 20050071405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Method and structure for producing high performance linear algebra routines using level 3 prefetching for kernel routines' [patent_app_type] => utility [patent_app_number] => 10/671889 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5297 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20050071405.pdf [firstpage_image] =>[orig_patent_app_number] => 10671889 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/671889
Method and structure for producing high performance linear algebra routines using level 3 prefetching for kernel routines Sep 28, 2003 Abandoned
Array ( [id] => 7676042 [patent_doc_number] => 20040153785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'System and method for enabling selective execution of computer code' [patent_app_type] => new [patent_app_number] => 10/629160 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4642 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153785.pdf [firstpage_image] =>[orig_patent_app_number] => 10629160 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/629160
System and method for enabling selective execution of computer code Jul 28, 2003 Abandoned
Array ( [id] => 5695738 [patent_doc_number] => 20060155885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Processor and a method in the processor, the processor comprising a programmable pipeline and at least one interface engine' [patent_app_type] => utility [patent_app_number] => 10/521586 [patent_app_country] => US [patent_app_date] => 2003-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3546 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20060155885.pdf [firstpage_image] =>[orig_patent_app_number] => 10521586 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/521586
Processor and a method in the processor, the processor comprising a programmable pipeline and at least one interface engine Jul 8, 2003 Abandoned
Array ( [id] => 5024734 [patent_doc_number] => 20070150701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Method and arrangement for power-efficient control of processors' [patent_app_type] => utility [patent_app_number] => 10/511575 [patent_app_country] => US [patent_app_date] => 2003-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2173 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20070150701.pdf [firstpage_image] =>[orig_patent_app_number] => 10511575 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/511575
Method and arrangement for power-efficient control of processors May 12, 2003 Abandoned
Array ( [id] => 5696157 [patent_doc_number] => 20060156304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Apparatus and method for scheduling tasks in a communications network' [patent_app_type] => utility [patent_app_number] => 10/513646 [patent_app_country] => US [patent_app_date] => 2003-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1564 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156304.pdf [firstpage_image] =>[orig_patent_app_number] => 10513646 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/513646
Apparatus and method for scheduling tasks in a communications network Apr 1, 2003 Abandoned
Array ( [id] => 8424611 [patent_doc_number] => 08281108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Reconfigurable general purpose processor having time restricted configurations' [patent_app_type] => utility [patent_app_number] => 10/501845 [patent_app_country] => US [patent_app_date] => 2003-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 6872 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10501845 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/501845
Reconfigurable general purpose processor having time restricted configurations Jan 19, 2003 Issued
Array ( [id] => 7445483 [patent_doc_number] => 20040003218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Branch prediction apparatus and branch prediction method' [patent_app_type] => new [patent_app_number] => 10/337360 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4401 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003218.pdf [firstpage_image] =>[orig_patent_app_number] => 10337360 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337360
Branch prediction apparatus and branch prediction method Jan 6, 2003 Abandoned
Array ( [id] => 5695824 [patent_doc_number] => 20060155971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Transmission of a digital message between a microprocessor monitoring circuit and an analysis tool' [patent_app_type] => utility [patent_app_number] => 10/535065 [patent_app_country] => US [patent_app_date] => 2002-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2718 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20060155971.pdf [firstpage_image] =>[orig_patent_app_number] => 10535065 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/535065
Transmission of a digital message between a microprocessor monitoring circuit and an analysis tool Nov 13, 2002 Abandoned
Array ( [id] => 6751999 [patent_doc_number] => 20030046520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Selective writing of data elements from packed data based upon a mask using predication' [patent_app_type] => new [patent_app_number] => 10/279553 [patent_app_country] => US [patent_app_date] => 2002-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3776 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20030046520.pdf [firstpage_image] =>[orig_patent_app_number] => 10279553 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279553
Selective writing of data elements from packed data based upon a mask using predication Oct 22, 2002 Abandoned
Array ( [id] => 6757487 [patent_doc_number] => 20030005264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Device and method for control of the data stream' [patent_app_type] => new [patent_app_number] => 10/169229 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2228 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20030005264.pdf [firstpage_image] =>[orig_patent_app_number] => 10169229 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/169229
Device and method for control of the data stream Jun 27, 2002 Abandoned
Array ( [id] => 4585773 [patent_doc_number] => 07856543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-21 [patent_title] => 'Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream' [patent_app_type] => utility [patent_app_number] => 10/073948 [patent_app_country] => US [patent_app_date] => 2002-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 17107 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/856/07856543.pdf [firstpage_image] =>[orig_patent_app_number] => 10073948 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/073948
Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream Feb 13, 2002 Issued
Array ( [id] => 8741129 [patent_doc_number] => 08412915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements' [patent_app_type] => utility [patent_app_number] => 09/997530 [patent_app_country] => US [patent_app_date] => 2001-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 12185 [patent_no_of_claims] => 124 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 09997530 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/997530
Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements Nov 29, 2001 Issued
Menu