Keith E. Vicary

Array ( [id] => 18622289 [patent_doc_number] => 11755330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Tracking exact convergence to guide the recovery process in response to a mispredicted branch [patent_app_type] => utility [patent_app_number] => 17/943341 [patent_app_country] => US [patent_app_date] => 2022-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9964 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19036383 [patent_doc_number] => 20240086198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => REGISTER REORGANISATION [patent_app_type] => utility [patent_app_number] => 17/943407 [patent_app_country] => US [patent_app_date] => 2022-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18889536 [patent_doc_number] => 11868306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Processing-in-memory concurrent processing system and method [patent_app_type] => utility [patent_app_number] => 17/943527 [patent_app_country] => US [patent_app_date] => 2022-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18356680 [patent_doc_number] => 11645080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Apparatuses, methods, and systems for instructions to request a history reset of a processor core [patent_app_type] => utility [patent_app_number] => 17/903307 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 28475 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17903307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19005849 [patent_doc_number] => 20240069920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => SECURING REGISTERS ACROSS SECURITY ZONES [patent_app_type] => utility [patent_app_number] => 17/897016 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20160148 [patent_doc_number] => 12386777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Processing-in-memory (PIM) device to perform a memory access operation and an arithmetic operation in response to a command from a PIM controller and a high speed interface, respectively [patent_app_type] => utility [patent_app_number] => 17/894014 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 64 [patent_no_of_words] => 44760 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19787289 [patent_doc_number] => 20250060968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => MULTI-LEVEL HYBRID ALGORITHM FILTERING-TYPE BRANCH PREDICTION METHOD AND PREDICTION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/684962 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4435 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18684962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18941725 [patent_doc_number] => 20240036864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => APPARATUS EMPLOYING WRAP TRACKING FOR ADDRESSING DATA OVERFLOW [patent_app_type] => utility [patent_app_number] => 17/816513 [patent_app_country] => US [patent_app_date] => 2022-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10718 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17816513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18007021 [patent_doc_number] => 20220365787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => EVENT HANDLING IN PIPELINE EXECUTE STAGES [patent_app_type] => utility [patent_app_number] => 17/876706 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17984570 [patent_doc_number] => 20220350607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => METHOD OF EXECUTING OPERATION, ELECTRONIC DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/867859 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18881278 [patent_doc_number] => 20240004647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => VECTOR PROCESSOR WITH VECTOR AND ELEMENT REDUCTION METHOD [patent_app_type] => utility [patent_app_number] => 17/855816 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19703881 [patent_doc_number] => 12197917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Exit history based branch prediction [patent_app_type] => utility [patent_app_number] => 17/849994 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9016 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18819513 [patent_doc_number] => 20230393853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => SELECTIVELY UPDATING BRANCH PREDICTORS FOR LOOPS EXECUTED FROM LOOP BUFFERS IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/832350 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19062161 [patent_doc_number] => 11941397 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-03-26 [patent_title] => Machine instructions for decoding acceleration including fuse input instructions to fuse multiple JPEG data blocks together to take advantage of a full SIMD width of a processor [patent_app_type] => utility [patent_app_number] => 17/804796 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 15389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19251006 [patent_doc_number] => 20240201996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => IMPROVEMENTS IN AND RELATING TO ENCODING AND COMPUTATION ON DISTRIBUTIONS OF DATA [patent_app_type] => utility [patent_app_number] => 18/562398 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18562398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18226739 [patent_doc_number] => 20230065733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => CALCULATOR AND CALCULATION METHOD [patent_app_type] => utility [patent_app_number] => 17/751880 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19375828 [patent_doc_number] => 12067398 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-08-20 [patent_title] => Shared learning table for load value prediction and load address prediction [patent_app_type] => utility [patent_app_number] => 17/661491 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18741697 [patent_doc_number] => 20230350678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => Instruction Set Architecture for Neural Network Quantization and Packing [patent_app_type] => utility [patent_app_number] => 17/732361 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17778607 [patent_doc_number] => 20220244957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => Cache Preload Operations Using Streaming Engine [patent_app_type] => utility [patent_app_number] => 17/720657 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17720657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17751457 [patent_doc_number] => 20220229662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => SUPER-THREAD PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/716981 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716981 [rel_patent_id] =>[rel_patent_doc_number] =>)