Search

Keith E. Vicary

Examiner (ID: 15210)

Most Active Art Unit
2183
Art Unit(s)
2182, 2183
Total Applications
804
Issued Applications
430
Pending Applications
77
Abandoned Applications
311

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18189302 [patent_doc_number] => 11579887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network [patent_app_type] => utility [patent_app_number] => 17/372439 [patent_app_country] => US [patent_app_date] => 2021-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 48 [patent_no_of_words] => 60868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372439
System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network Jul 9, 2021 Issued
Array ( [id] => 18096079 [patent_doc_number] => 20220414420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => ULTRA-LOW-POWER AND LOW-AREA SOLUTION OF BINARY MULTIPLY-ACCUMULATE SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/360986 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360986 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/360986
ULTRA-LOW-POWER AND LOW-AREA SOLUTION OF BINARY MULTIPLY-ACCUMULATE SYSTEM AND METHOD Jun 27, 2021 Pending
Array ( [id] => 18095508 [patent_doc_number] => 20220413849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => PROVIDING ATOMICITY FOR COMPLEX OPERATIONS USING NEAR-MEMORY COMPUTING [patent_app_type] => utility [patent_app_number] => 17/360949 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360949 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/360949
PROVIDING ATOMICITY FOR COMPLEX OPERATIONS USING NEAR-MEMORY COMPUTING Jun 27, 2021 Abandoned
Array ( [id] => 19427174 [patent_doc_number] => 12086597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Array processor using programmable per-dimension size values and programmable per-dimension stride values for memory configuration [patent_app_type] => utility [patent_app_number] => 17/361250 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 12297 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361250 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361250
Array processor using programmable per-dimension size values and programmable per-dimension stride values for memory configuration Jun 27, 2021 Issued
Array ( [id] => 18095509 [patent_doc_number] => 20220413850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => Apparatus for Processor with Macro-Instruction and Associated Methods [patent_app_type] => utility [patent_app_number] => 17/361244 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361244 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361244
Processor with macro-instruction achieving zero-latency data movement Jun 27, 2021 Issued
Array ( [id] => 18095708 [patent_doc_number] => 20220414049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => Apparatus for Array Processor and Associated Methods [patent_app_type] => utility [patent_app_number] => 17/361240 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361240 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361240
Array processor having an instruction sequencer including a program state controller and loop controllers Jun 27, 2021 Issued
Array ( [id] => 18095527 [patent_doc_number] => 20220413868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => FAST PERFECT ISSUE OF DEPENDENT INSTRUCTIONS IN A DISTRIBUTED ISSUE QUEUE SYSTEM [patent_app_type] => utility [patent_app_number] => 17/358183 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358183 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/358183
Fast perfect issue of dependent instructions in a distributed issue queue system Jun 24, 2021 Issued
Array ( [id] => 17157832 [patent_doc_number] => 20210318883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => APPARATUS AND METHOD FOR WRITING BACK INSTRUCTION EXECUTION RESULT AND PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/343139 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343139 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/343139
APPARATUS AND METHOD FOR WRITING BACK INSTRUCTION EXECUTION RESULT AND PROCESSING APPARATUS Jun 8, 2021 Abandoned
Array ( [id] => 18067012 [patent_doc_number] => 20220398100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => PROCESSORS EMPLOYING MEMORY DATA BYPASSING IN MEMORY DATA DEPENDENT INSTRUCTIONS AS A STORE DATA FORWARDING MECHANISM, AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/343442 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343442 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/343442
PROCESSORS EMPLOYING MEMORY DATA BYPASSING IN MEMORY DATA DEPENDENT INSTRUCTIONS AS A STORE DATA FORWARDING MECHANISM, AND RELATED METHODS Jun 8, 2021 Abandoned
Array ( [id] => 17230659 [patent_doc_number] => 20210357216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => ENABLING REMOVAL AND RECONSTRUCTION OF FLAG OPERATIONS IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/335284 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335284 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/335284
Enabling removal and reconstruction of flag operations in a processor May 31, 2021 Issued
Array ( [id] => 18136116 [patent_doc_number] => 11561794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry [patent_app_type] => utility [patent_app_number] => 17/331085 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 14617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331085
Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry May 25, 2021 Issued
Array ( [id] => 17245523 [patent_doc_number] => 20210365267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => METHOD AND APPARATUS FOR INSTRUCTION EXPANSION FOR EMBEDDED DEVICE [patent_app_type] => utility [patent_app_number] => 17/326132 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326132
METHOD AND APPARATUS FOR INSTRUCTION EXPANSION FOR EMBEDDED DEVICE May 19, 2021 Abandoned
Array ( [id] => 17977331 [patent_doc_number] => 11494191 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-08 [patent_title] => Tracking exact convergence to guide the recovery process in response to a mispredicted branch [patent_app_type] => utility [patent_app_number] => 17/323069 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9918 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323069 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323069
Tracking exact convergence to guide the recovery process in response to a mispredicted branch May 17, 2021 Issued
Array ( [id] => 18234803 [patent_doc_number] => 11599361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Flushing a fetch queue using predecode circuitry and prediction information [patent_app_type] => utility [patent_app_number] => 17/315737 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8085 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315737
Flushing a fetch queue using predecode circuitry and prediction information May 9, 2021 Issued
Array ( [id] => 17202573 [patent_doc_number] => 20210342668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => Methods And Systems For Efficient Processing Of Recurrent Neural Networks [patent_app_type] => utility [patent_app_number] => 17/244797 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17244797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/244797
Methods And Systems For Efficient Processing Of Recurrent Neural Networks Apr 28, 2021 Pending
Array ( [id] => 19114803 [patent_doc_number] => 20240126553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => DATA PROCESSING METHOD AND APPARATUS, AND RELATED PRODUCT [patent_app_type] => utility [patent_app_number] => 17/619781 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17619781 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/619781
DATA PROCESSING METHOD AND APPARATUS, AND RELATED PRODUCT Apr 27, 2021 Pending
Array ( [id] => 17977330 [patent_doc_number] => 11494190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Circuitry and method for controlling a generated association of a physical register with a predicated processing operation based on predicate data state [patent_app_type] => utility [patent_app_number] => 17/218371 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5928 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/218371
Circuitry and method for controlling a generated association of a physical register with a predicated processing operation based on predicate data state Mar 30, 2021 Issued
Array ( [id] => 17915616 [patent_doc_number] => 20220318012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => PROCESSING-IN-MEMORY CONCURRENT PROCESSING SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/217792 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217792 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/217792
Processing-in-memory concurrent processing system and method Mar 29, 2021 Issued
Array ( [id] => 17899226 [patent_doc_number] => 20220308888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => METHOD FOR REDUCING LOST CYCLES AFTER BRANCH MISPREDICTION IN A MULTI-THREAD MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 17/214805 [patent_app_country] => US [patent_app_date] => 2021-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214805 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214805
METHOD FOR REDUCING LOST CYCLES AFTER BRANCH MISPREDICTION IN A MULTI-THREAD MICROPROCESSOR Mar 26, 2021 Abandoned
Array ( [id] => 17899225 [patent_doc_number] => 20220308887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => MITIGATION OF BRANCH MISPREDICTION PENALTY IN A HARDWARE MULTI-THREAD MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 17/214802 [patent_app_country] => US [patent_app_date] => 2021-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214802
MITIGATION OF BRANCH MISPREDICTION PENALTY IN A HARDWARE MULTI-THREAD MICROPROCESSOR Mar 26, 2021 Abandoned
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