Search

Kendra Ly

Examiner (ID: 3805, Phone: (571)270-7060 , Office: P/1747 )

Most Active Art Unit
1749
Art Unit(s)
1749, 1747
Total Applications
657
Issued Applications
363
Pending Applications
73
Abandoned Applications
240

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16162655 [patent_doc_number] => 20200219560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/556288 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16556288 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/556288
Semiconductor memory device Aug 29, 2019 Issued
Array ( [id] => 16417590 [patent_doc_number] => 10825490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 16/556044 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11084 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16556044 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/556044
Semiconductor storage device Aug 28, 2019 Issued
Array ( [id] => 16684181 [patent_doc_number] => 10943670 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-09 [patent_title] => Dummy wordline design techniques [patent_app_type] => utility [patent_app_number] => 16/555964 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555964 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555964
Dummy wordline design techniques Aug 28, 2019 Issued
Array ( [id] => 16447959 [patent_doc_number] => 10839890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Apparatuses and methods for subrow addressing [patent_app_type] => utility [patent_app_number] => 16/551854 [patent_app_country] => US [patent_app_date] => 2019-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11507 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16551854 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/551854
Apparatuses and methods for subrow addressing Aug 26, 2019 Issued
Array ( [id] => 16536271 [patent_doc_number] => 10878884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Apparatuses and methods to reverse data stored in memory [patent_app_type] => utility [patent_app_number] => 16/550609 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10655 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550609 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/550609
Apparatuses and methods to reverse data stored in memory Aug 25, 2019 Issued
Array ( [id] => 16624588 [patent_doc_number] => 20210043241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => Polarity Swapping Circuitry [patent_app_type] => utility [patent_app_number] => 16/534942 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16534942 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/534942
Polarity swapping circuitry Aug 6, 2019 Issued
Array ( [id] => 15370181 [patent_doc_number] => 20200020855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => TAPERED MEMORY CELL PROFILES [patent_app_type] => utility [patent_app_number] => 16/534937 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13496 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16534937 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/534937
Tapered memory cell profiles Aug 6, 2019 Issued
Array ( [id] => 16495737 [patent_doc_number] => 10861787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-08 [patent_title] => Memory device with bitline noise suppressing scheme [patent_app_type] => utility [patent_app_number] => 16/534120 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4809 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16534120 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/534120
Memory device with bitline noise suppressing scheme Aug 6, 2019 Issued
Array ( [id] => 16386266 [patent_doc_number] => 10811107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Semiconductor memory device and memory system having the same [patent_app_type] => utility [patent_app_number] => 16/531926 [patent_app_country] => US [patent_app_date] => 2019-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9786 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16531926 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/531926
Semiconductor memory device and memory system having the same Aug 4, 2019 Issued
Array ( [id] => 16637813 [patent_doc_number] => 10916327 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-09 [patent_title] => Apparatuses and methods for fuse latch and match circuits [patent_app_type] => utility [patent_app_number] => 16/531492 [patent_app_country] => US [patent_app_date] => 2019-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16531492 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/531492
Apparatuses and methods for fuse latch and match circuits Aug 4, 2019 Issued
Array ( [id] => 16638033 [patent_doc_number] => 10916548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-09 [patent_title] => Memory arrays with vertical access transistors [patent_app_type] => utility [patent_app_number] => 16/522336 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10108 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16522336 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/522336
Memory arrays with vertical access transistors Jul 24, 2019 Issued
Array ( [id] => 16536281 [patent_doc_number] => 10878894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Memory device having low bitline voltage swing in read port and method for reading memory cell [patent_app_type] => utility [patent_app_number] => 16/521446 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5597 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521446 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521446
Memory device having low bitline voltage swing in read port and method for reading memory cell Jul 23, 2019 Issued
Array ( [id] => 16653141 [patent_doc_number] => 10930332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Memory array with individually trimmable sense amplifiers [patent_app_type] => utility [patent_app_number] => 16/520162 [patent_app_country] => US [patent_app_date] => 2019-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6042 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16520162 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/520162
Memory array with individually trimmable sense amplifiers Jul 22, 2019 Issued
Array ( [id] => 15029925 [patent_doc_number] => 20190325967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => DATA ERASURE DEVICE FOR ERASING DATA FROM NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/502924 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5011 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16502924 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/502924
Data erasure device for erasing data from non-volatile semiconductor memory device and method for manufacturing non-volatile semiconductor memory device Jul 2, 2019 Issued
Array ( [id] => 15806957 [patent_doc_number] => 20200126621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 16/458222 [patent_app_country] => US [patent_app_date] => 2019-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458222 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458222
Nonvolatile memory device and operating method of the same Jun 30, 2019 Issued
Array ( [id] => 16544664 [patent_doc_number] => 20200411079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => HIGH BANDWIDTH DESTRUCTIVE READ EMBEDDED MEMORY [patent_app_type] => utility [patent_app_number] => 16/458022 [patent_app_country] => US [patent_app_date] => 2019-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458022 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458022
High bandwidth destructive read embedded memory Jun 28, 2019 Issued
Array ( [id] => 15029865 [patent_doc_number] => 20190325937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => MULTI-PHASE CLOCK DIVISION [patent_app_type] => utility [patent_app_number] => 16/457403 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457403 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/457403
Multi-phase clock division Jun 27, 2019 Issued
Array ( [id] => 16544679 [patent_doc_number] => 20200411094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => D-MRAM DEVICES AND METHODS FOR REPLICATING DATA AND READ AND WRITE OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/457808 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457808 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/457808
D-MRAM devices and methods for replicating data and read and write operations Jun 27, 2019 Issued
Array ( [id] => 14968577 [patent_doc_number] => 20190311767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => Memory Cells, Memory Systems, and Memory Programming Methods [patent_app_type] => utility [patent_app_number] => 16/437997 [patent_app_country] => US [patent_app_date] => 2019-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16437997 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/437997
Memory cells, memory systems, and memory programming methods Jun 10, 2019 Issued
Array ( [id] => 16462900 [patent_doc_number] => 10846248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same [patent_app_type] => utility [patent_app_number] => 16/432413 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5122 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432413 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432413
Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same Jun 4, 2019 Issued
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