Search

Kendra Ly

Examiner (ID: 3805, Phone: (571)270-7060 , Office: P/1747 )

Most Active Art Unit
1749
Art Unit(s)
1749, 1747
Total Applications
657
Issued Applications
363
Pending Applications
73
Abandoned Applications
240

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8944973 [patent_doc_number] => 08498156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Memory cell structures and methods' [patent_app_type] => utility [patent_app_number] => 13/554278 [patent_app_country] => US [patent_app_date] => 2012-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5302 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13554278 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/554278
Memory cell structures and methods Jul 19, 2012 Issued
Array ( [id] => 9010905 [patent_doc_number] => 08526216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Memory device and manufacturing method the same' [patent_app_type] => utility [patent_app_number] => 13/546013 [patent_app_country] => US [patent_app_date] => 2012-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9528 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13546013 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/546013
Memory device and manufacturing method the same Jul 10, 2012 Issued
Array ( [id] => 8475830 [patent_doc_number] => 20120275237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'MEMORY CONTROLLER HAVING A WRITE-TIMING CALIBRATION MODE' [patent_app_type] => utility [patent_app_number] => 13/544967 [patent_app_country] => US [patent_app_date] => 2012-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11365 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13544967 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/544967
Memory controller having a write-timing calibration mode Jul 8, 2012 Issued
Array ( [id] => 8494657 [patent_doc_number] => 20120294065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-22 [patent_title] => 'VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/469740 [patent_app_country] => US [patent_app_date] => 2012-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7178 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13469740 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/469740
Variable resistance memory device and method of fabricating the same May 10, 2012 Issued
Array ( [id] => 9146851 [patent_doc_number] => 20130301374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'WORD LINE DRIVER HAVING A CONTROL SWITCH' [patent_app_type] => utility [patent_app_number] => 13/466518 [patent_app_country] => US [patent_app_date] => 2012-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13466518 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/466518
Word line driver having a control switch May 7, 2012 Issued
Array ( [id] => 9251122 [patent_doc_number] => 08614909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-24 [patent_title] => 'Internal supply testing in memory devices configured for stacked arrangements' [patent_app_type] => utility [patent_app_number] => 13/466736 [patent_app_country] => US [patent_app_date] => 2012-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 17813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13466736 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/466736
Internal supply testing in memory devices configured for stacked arrangements May 7, 2012 Issued
Array ( [id] => 9442523 [patent_doc_number] => 08711646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Architecture, system and method for testing resistive type memory' [patent_app_type] => utility [patent_app_number] => 13/466922 [patent_app_country] => US [patent_app_date] => 2012-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11273 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13466922 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/466922
Architecture, system and method for testing resistive type memory May 7, 2012 Issued
Array ( [id] => 9133431 [patent_doc_number] => 20130294145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'SWITCHING DEVICE STRUCTURES AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/465596 [patent_app_country] => US [patent_app_date] => 2012-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4292 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13465596 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/465596
Switching device structures and methods May 6, 2012 Issued
Array ( [id] => 9356877 [patent_doc_number] => 08675423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Apparatuses and methods including supply current in memory' [patent_app_type] => utility [patent_app_number] => 13/465632 [patent_app_country] => US [patent_app_date] => 2012-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11791 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13465632 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/465632
Apparatuses and methods including supply current in memory May 6, 2012 Issued
Array ( [id] => 9234288 [patent_doc_number] => 08599597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'Circuits configured to remain in a non-program state during a power-down event' [patent_app_type] => utility [patent_app_number] => 13/465132 [patent_app_country] => US [patent_app_date] => 2012-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8978 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13465132 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/465132
Circuits configured to remain in a non-program state during a power-down event May 6, 2012 Issued
Array ( [id] => 9287753 [patent_doc_number] => 08644093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Writing circuit, semiconductor integrated circuit and writing method' [patent_app_type] => utility [patent_app_number] => 13/465096 [patent_app_country] => US [patent_app_date] => 2012-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9754 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13465096 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/465096
Writing circuit, semiconductor integrated circuit and writing method May 6, 2012 Issued
Array ( [id] => 9609899 [patent_doc_number] => 08787079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Reading data from multi-level cell memory' [patent_app_type] => utility [patent_app_number] => 13/465308 [patent_app_country] => US [patent_app_date] => 2012-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7822 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13465308 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/465308
Reading data from multi-level cell memory May 6, 2012 Issued
Array ( [id] => 9133464 [patent_doc_number] => 20130294178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'METHOD FOR REDUCING STANDBY CURRENT OF SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/464998 [patent_app_country] => US [patent_app_date] => 2012-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3896 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464998 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/464998
Method for reducing standby current of semiconductor memory device May 5, 2012 Issued
Array ( [id] => 9779659 [patent_doc_number] => 08854873 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-07 [patent_title] => 'Memory devices, architectures and methods for memory elements having dynamic change in property' [patent_app_type] => utility [patent_app_number] => 13/464926 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 50 [patent_no_of_words] => 12647 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464926 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/464926
Memory devices, architectures and methods for memory elements having dynamic change in property May 3, 2012 Issued
Array ( [id] => 9141880 [patent_doc_number] => 08582354 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-12 [patent_title] => 'Method and apparatus for testing a resistive memory element' [patent_app_type] => utility [patent_app_number] => 13/464060 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7432 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464060 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/464060
Method and apparatus for testing a resistive memory element May 3, 2012 Issued
Array ( [id] => 9442514 [patent_doc_number] => 08711636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Method of operating a split gate flash memory cell with coupling gate' [patent_app_type] => utility [patent_app_number] => 13/463558 [patent_app_country] => US [patent_app_date] => 2012-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2051 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463558 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/463558
Method of operating a split gate flash memory cell with coupling gate May 2, 2012 Issued
Array ( [id] => 9377278 [patent_doc_number] => 08681548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Column redundancy circuitry for non-volatile memory' [patent_app_type] => utility [patent_app_number] => 13/463422 [patent_app_country] => US [patent_app_date] => 2012-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 10030 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463422 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/463422
Column redundancy circuitry for non-volatile memory May 2, 2012 Issued
Array ( [id] => 9346506 [patent_doc_number] => 08665660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Clock handoff circuit and clock handoff method' [patent_app_type] => utility [patent_app_number] => 13/463224 [patent_app_country] => US [patent_app_date] => 2012-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6388 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463224 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/463224
Clock handoff circuit and clock handoff method May 2, 2012 Issued
Array ( [id] => 9470750 [patent_doc_number] => 08724393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Thermally assisted flash memory with diode strapping' [patent_app_type] => utility [patent_app_number] => 13/458970 [patent_app_country] => US [patent_app_date] => 2012-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 65 [patent_no_of_words] => 22122 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13458970 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/458970
Thermally assisted flash memory with diode strapping Apr 26, 2012 Issued
Array ( [id] => 8565148 [patent_doc_number] => 20120327719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'THERMALLY ASSISTED FLASH MEMORY WITH SEGMENTED WORD LINES' [patent_app_type] => utility [patent_app_number] => 13/458975 [patent_app_country] => US [patent_app_date] => 2012-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 62 [patent_no_of_words] => 22125 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13458975 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/458975
Thermally assisted flash memory with segmented word lines Apr 26, 2012 Issued
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