Search

Kendra Ly

Examiner (ID: 3805, Phone: (571)270-7060 , Office: P/1747 )

Most Active Art Unit
1749
Art Unit(s)
1749, 1747
Total Applications
657
Issued Applications
363
Pending Applications
73
Abandoned Applications
240

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4458939 [patent_doc_number] => 07894232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Semiconductor device having user field and vendor field' [patent_app_type] => utility [patent_app_number] => 12/427392 [patent_app_country] => US [patent_app_date] => 2009-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 10162 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/894/07894232.pdf [firstpage_image] =>[orig_patent_app_number] => 12427392 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/427392
Semiconductor device having user field and vendor field Apr 20, 2009 Issued
Array ( [id] => 6240719 [patent_doc_number] => 20100268865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'Static Wear Leveling' [patent_app_type] => utility [patent_app_number] => 12/426924 [patent_app_country] => US [patent_app_date] => 2009-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20100268865.pdf [firstpage_image] =>[orig_patent_app_number] => 12426924 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/426924
Static wear leveling Apr 19, 2009 Issued
Array ( [id] => 5556957 [patent_doc_number] => 20090268534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/426624 [patent_app_country] => US [patent_app_date] => 2009-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5496 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20090268534.pdf [firstpage_image] =>[orig_patent_app_number] => 12426624 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/426624
Semiconductor memory device and test method thereof Apr 19, 2009 Issued
Array ( [id] => 4581154 [patent_doc_number] => 07855923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-21 [patent_title] => 'Write current compensation using word line boosting circuitry' [patent_app_type] => utility [patent_app_number] => 12/426098 [patent_app_country] => US [patent_app_date] => 2009-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/855/07855923.pdf [firstpage_image] =>[orig_patent_app_number] => 12426098 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/426098
Write current compensation using word line boosting circuitry Apr 16, 2009 Issued
Array ( [id] => 6233455 [patent_doc_number] => 20100265774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'METHOD FOR DETERMINING NATIVE THRESHOLD VOLTAGE OF NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/425650 [patent_app_country] => US [patent_app_date] => 2009-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2707 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20100265774.pdf [firstpage_image] =>[orig_patent_app_number] => 12425650 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/425650
Method for determining native threshold voltage of nonvolatile memory Apr 16, 2009 Issued
Array ( [id] => 6348442 [patent_doc_number] => 20100085796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'Enhancing Read and Write Sense Margins in a Resistive Sense Element' [patent_app_type] => utility [patent_app_number] => 12/425856 [patent_app_country] => US [patent_app_date] => 2009-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20100085796.pdf [firstpage_image] =>[orig_patent_app_number] => 12425856 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/425856
Enhancing read and write sense margins in a resistive sense element Apr 16, 2009 Issued
Array ( [id] => 6233381 [patent_doc_number] => 20100265749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'THREE DIMENSIONALLY STACKED NON VOLATILE MEMORY UNITS' [patent_app_type] => utility [patent_app_number] => 12/425084 [patent_app_country] => US [patent_app_date] => 2009-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9533 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20100265749.pdf [firstpage_image] =>[orig_patent_app_number] => 12425084 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/425084
Three dimensionally stacked non volatile memory units Apr 15, 2009 Issued
Array ( [id] => 4559946 [patent_doc_number] => 07961530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Semiconductor device including nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 12/424814 [patent_app_country] => US [patent_app_date] => 2009-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7231 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/961/07961530.pdf [firstpage_image] =>[orig_patent_app_number] => 12424814 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/424814
Semiconductor device including nonvolatile memory Apr 15, 2009 Issued
Array ( [id] => 4540858 [patent_doc_number] => 07872898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-18 [patent_title] => 'One time programmable read only memory and programming method thereof' [patent_app_type] => utility [patent_app_number] => 12/423810 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 6135 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/872/07872898.pdf [firstpage_image] =>[orig_patent_app_number] => 12423810 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/423810
One time programmable read only memory and programming method thereof Apr 14, 2009 Issued
Array ( [id] => 4503803 [patent_doc_number] => 07948792 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-24 [patent_title] => 'Memory and techniques for using same' [patent_app_type] => utility [patent_app_number] => 12/424362 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6222 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948792.pdf [firstpage_image] =>[orig_patent_app_number] => 12424362 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/424362
Memory and techniques for using same Apr 14, 2009 Issued
Array ( [id] => 6494998 [patent_doc_number] => 20100260000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'Low-Power Operation of Static Memory in a Read-Only Mode' [patent_app_type] => utility [patent_app_number] => 12/423378 [patent_app_country] => US [patent_app_date] => 2009-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8380 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20100260000.pdf [firstpage_image] =>[orig_patent_app_number] => 12423378 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/423378
Low-power operation of static memory in a read-only mode Apr 13, 2009 Issued
Array ( [id] => 4625571 [patent_doc_number] => 08004877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Fault tolerant asynchronous circuits' [patent_app_type] => utility [patent_app_number] => 12/405746 [patent_app_country] => US [patent_app_date] => 2009-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5978 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004877.pdf [firstpage_image] =>[orig_patent_app_number] => 12405746 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/405746
Fault tolerant asynchronous circuits Mar 16, 2009 Issued
Array ( [id] => 6537206 [patent_doc_number] => 20100232202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'DUAL PORT MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/404892 [patent_app_country] => US [patent_app_date] => 2009-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6830 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20100232202.pdf [firstpage_image] =>[orig_patent_app_number] => 12404892 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/404892
Dual port memory device Mar 15, 2009 Issued
Array ( [id] => 6361115 [patent_doc_number] => 20100073991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'STORAGE APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/404510 [patent_app_country] => US [patent_app_date] => 2009-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9816 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20100073991.pdf [firstpage_image] =>[orig_patent_app_number] => 12404510 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/404510
Storage apparatus including non-volatile SRAM Mar 15, 2009 Issued
Array ( [id] => 5484229 [patent_doc_number] => 20090273994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'DUAL MODE ACCESSING SIGNAL CONTROL APPARATUS AND DUAL MODE TIMING SIGNAL GENERATING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/403860 [patent_app_country] => US [patent_app_date] => 2009-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4452 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20090273994.pdf [firstpage_image] =>[orig_patent_app_number] => 12403860 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/403860
Dual mode accessing signal control apparatus and dual mode timing signal generating apparatus Mar 12, 2009 Issued
Array ( [id] => 5457145 [patent_doc_number] => 20090257297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'MULTI-CHIP SEMICONDUCTOR DEVICE PROVIDING ENHANCED REDUNDANCY CAPABILITIES' [patent_app_type] => utility [patent_app_number] => 12/402660 [patent_app_country] => US [patent_app_date] => 2009-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3408 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20090257297.pdf [firstpage_image] =>[orig_patent_app_number] => 12402660 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/402660
Multi-chip semiconductor device providing enhanced redundancy capabilities Mar 11, 2009 Issued
Array ( [id] => 4590551 [patent_doc_number] => 07852701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-14 [patent_title] => 'Circuits for and methods of determining a period of time during which a device was without power' [patent_app_type] => utility [patent_app_number] => 12/402362 [patent_app_country] => US [patent_app_date] => 2009-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 8554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/852/07852701.pdf [firstpage_image] =>[orig_patent_app_number] => 12402362 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/402362
Circuits for and methods of determining a period of time during which a device was without power Mar 10, 2009 Issued
Array ( [id] => 5526023 [patent_doc_number] => 20090196100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'SYSTEMS AND METHODS FOR REDUCING UNAUTHORIZED DATA RECOVERY FROM SOLID-STATE STORAGE DEVICES' [patent_app_type] => utility [patent_app_number] => 12/399654 [patent_app_country] => US [patent_app_date] => 2009-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6515 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20090196100.pdf [firstpage_image] =>[orig_patent_app_number] => 12399654 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/399654
Systems and methods for reducing unauthorized data recovery from solid-state storage devices Mar 5, 2009 Issued
Array ( [id] => 5433986 [patent_doc_number] => 20090168572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 12/394550 [patent_app_country] => US [patent_app_date] => 2009-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4768 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20090168572.pdf [firstpage_image] =>[orig_patent_app_number] => 12394550 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/394550
Semiconductor memory Feb 26, 2009 Issued
Array ( [id] => 5513340 [patent_doc_number] => 20090213646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'Phase-change random access memories capable of suppressing coupling noise during read-while-write operation' [patent_app_type] => utility [patent_app_number] => 12/379398 [patent_app_country] => US [patent_app_date] => 2009-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5333 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20090213646.pdf [firstpage_image] =>[orig_patent_app_number] => 12379398 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/379398
Phase-change random access memories capable of suppressing coupling noise during read-while-write operation Feb 19, 2009 Issued
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