Search

Kendra Ly

Examiner (ID: 3805, Phone: (571)270-7060 , Office: P/1747 )

Most Active Art Unit
1749
Art Unit(s)
1749, 1747
Total Applications
657
Issued Applications
363
Pending Applications
73
Abandoned Applications
240

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5408702 [patent_doc_number] => 20090122600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'NONVOLATILE MEMORY USING RESISTANCE MATERIAL' [patent_app_type] => utility [patent_app_number] => 12/243578 [patent_app_country] => US [patent_app_date] => 2008-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5503 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20090122600.pdf [firstpage_image] =>[orig_patent_app_number] => 12243578 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/243578
Nonvolatile memory using resistance material Sep 30, 2008 Issued
Array ( [id] => 5523114 [patent_doc_number] => 20090031095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'PURGE OPERATIONS FOR SOLID-STATE STORAGE DEVICES' [patent_app_type] => utility [patent_app_number] => 12/240579 [patent_app_country] => US [patent_app_date] => 2008-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6539 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20090031095.pdf [firstpage_image] =>[orig_patent_app_number] => 12240579 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/240579
Purge operations for solid-state storage devices Sep 28, 2008 Issued
Array ( [id] => 5289272 [patent_doc_number] => 20090022002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/212066 [patent_app_country] => US [patent_app_date] => 2008-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9802 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20090022002.pdf [firstpage_image] =>[orig_patent_app_number] => 12212066 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/212066
Semiconductor memory device Sep 16, 2008 Issued
Array ( [id] => 5507051 [patent_doc_number] => 20090080258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'ERASE METHOD IN THIN FILM NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/211764 [patent_app_country] => US [patent_app_date] => 2008-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2887 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20090080258.pdf [firstpage_image] =>[orig_patent_app_number] => 12211764 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/211764
ERASE METHOD IN THIN FILM NONVOLATILE MEMORY Sep 15, 2008 Abandoned
Array ( [id] => 56324 [patent_doc_number] => 07768824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Magnetoresistive element and magnetoresistive random access memory including the same' [patent_app_type] => utility [patent_app_number] => 12/211388 [patent_app_country] => US [patent_app_date] => 2008-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12226 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/768/07768824.pdf [firstpage_image] =>[orig_patent_app_number] => 12211388 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/211388
Magnetoresistive element and magnetoresistive random access memory including the same Sep 15, 2008 Issued
Array ( [id] => 4584440 [patent_doc_number] => 07826255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Variable write and read methods for resistive random access memory' [patent_app_type] => utility [patent_app_number] => 12/210526 [patent_app_country] => US [patent_app_date] => 2008-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4506 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826255.pdf [firstpage_image] =>[orig_patent_app_number] => 12210526 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/210526
Variable write and read methods for resistive random access memory Sep 14, 2008 Issued
Array ( [id] => 4515235 [patent_doc_number] => 07916547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Method for controlling a non-volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/209486 [patent_app_country] => US [patent_app_date] => 2008-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 32 [patent_no_of_words] => 11029 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/916/07916547.pdf [firstpage_image] =>[orig_patent_app_number] => 12209486 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/209486
Method for controlling a non-volatile semiconductor memory device Sep 11, 2008 Issued
Array ( [id] => 5500761 [patent_doc_number] => 20090161449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/209748 [patent_app_country] => US [patent_app_date] => 2008-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20090161449.pdf [firstpage_image] =>[orig_patent_app_number] => 12209748 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/209748
Semiconductor storage device Sep 11, 2008 Issued
Array ( [id] => 4500732 [patent_doc_number] => 07957178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Storage cell having buffer circuit for driving the bitline' [patent_app_type] => utility [patent_app_number] => 12/209418 [patent_app_country] => US [patent_app_date] => 2008-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6928 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/957/07957178.pdf [firstpage_image] =>[orig_patent_app_number] => 12209418 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/209418
Storage cell having buffer circuit for driving the bitline Sep 11, 2008 Issued
Array ( [id] => 84235 [patent_doc_number] => 07746704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-29 [patent_title] => 'Program-and-erase method for multilevel nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 12/209794 [patent_app_country] => US [patent_app_date] => 2008-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 12539 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/746/07746704.pdf [firstpage_image] =>[orig_patent_app_number] => 12209794 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/209794
Program-and-erase method for multilevel nonvolatile memory Sep 11, 2008 Issued
Array ( [id] => 6298465 [patent_doc_number] => 20100067285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'NOVEL SENSING CIRCUIT FOR PCRAM APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 12/209920 [patent_app_country] => US [patent_app_date] => 2008-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6786 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20100067285.pdf [firstpage_image] =>[orig_patent_app_number] => 12209920 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/209920
Sensing circuit for PCRAM applications Sep 11, 2008 Issued
Array ( [id] => 105299 [patent_doc_number] => 07724596 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-25 [patent_title] => 'Auto-zero current sensing amplifier' [patent_app_type] => utility [patent_app_number] => 12/209577 [patent_app_country] => US [patent_app_date] => 2008-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 8328 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/724/07724596.pdf [firstpage_image] =>[orig_patent_app_number] => 12209577 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/209577
Auto-zero current sensing amplifier Sep 11, 2008 Issued
Array ( [id] => 6298479 [patent_doc_number] => 20100067293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'Programmable and Redundant Circuitry Based On Magnetic Tunnel Junction (MTJ)' [patent_app_type] => utility [patent_app_number] => 12/210126 [patent_app_country] => US [patent_app_date] => 2008-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3304 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20100067293.pdf [firstpage_image] =>[orig_patent_app_number] => 12210126 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/210126
Programmable and redundant circuitry based on magnetic tunnel junction (MTJ) Sep 11, 2008 Issued
Array ( [id] => 5295157 [patent_doc_number] => 20090010083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'CLOCK CIRCUITRY FOR DDR-SDRAM MEMORY CONTROLLER' [patent_app_type] => utility [patent_app_number] => 12/207147 [patent_app_country] => US [patent_app_date] => 2008-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7937 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20090010083.pdf [firstpage_image] =>[orig_patent_app_number] => 12207147 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/207147
Clock circuitry for DDR-SDRAM memory controller Sep 8, 2008 Issued
Array ( [id] => 154433 [patent_doc_number] => 07679953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Calibration system for writing and reading multiple states into phase change memory' [patent_app_type] => utility [patent_app_number] => 12/283041 [patent_app_country] => US [patent_app_date] => 2008-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 7636 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/679/07679953.pdf [firstpage_image] =>[orig_patent_app_number] => 12283041 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/283041
Calibration system for writing and reading multiple states into phase change memory Sep 8, 2008 Issued
Array ( [id] => 4565224 [patent_doc_number] => 07821856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Memory device having an evaluation circuit' [patent_app_type] => utility [patent_app_number] => 12/201192 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4773 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/821/07821856.pdf [firstpage_image] =>[orig_patent_app_number] => 12201192 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/201192
Memory device having an evaluation circuit Aug 28, 2008 Issued
Array ( [id] => 4851095 [patent_doc_number] => 20080316837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CONTROLLING POTENTIAL LEVEL OF POWER SUPPLY LINE AND/OR GROUND LINE' [patent_app_type] => utility [patent_app_number] => 12/195038 [patent_app_country] => US [patent_app_date] => 2008-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 22569 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0316/20080316837.pdf [firstpage_image] =>[orig_patent_app_number] => 12195038 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/195038
SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CONTROLLING POTENTIAL LEVEL OF POWER SUPPLY LINE AND/OR GROUND LINE Aug 19, 2008 Abandoned
Array ( [id] => 6078137 [patent_doc_number] => 20110141799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'REVERSING A POTENTIAL POLARITY FOR READING PHASE-CHANGE CELLS TO SHORTEN A RECOVERY DELAY AFTER PROGRAMMING' [patent_app_type] => utility [patent_app_number] => 12/992062 [patent_app_country] => US [patent_app_date] => 2008-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2205 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20110141799.pdf [firstpage_image] =>[orig_patent_app_number] => 12992062 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/992062
Reversing a potential polarity for reading phase-change cells to shorten a recovery delay after programming Jul 28, 2008 Issued
Array ( [id] => 8167496 [patent_doc_number] => 08174923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Voltage-stepped low-power memory device' [patent_app_type] => utility [patent_app_number] => 12/680986 [patent_app_country] => US [patent_app_date] => 2008-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8460 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/174/08174923.pdf [firstpage_image] =>[orig_patent_app_number] => 12680986 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/680986
Voltage-stepped low-power memory device Jul 21, 2008 Issued
Array ( [id] => 6475099 [patent_doc_number] => 20100008176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Write Leveling Of Memory Units Designed To Receive Access Requests In A Sequential Chained Topology' [patent_app_type] => utility [patent_app_number] => 12/169662 [patent_app_country] => US [patent_app_date] => 2008-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20100008176.pdf [firstpage_image] =>[orig_patent_app_number] => 12169662 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/169662
Write leveling of memory units designed to receive access requests in a sequential chained topology Jul 8, 2008 Issued
Menu